Datasheet

628
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
41.3 AT91SAM7X512 Errata - Rev. A Parts
Refer to Section 41.1 ”Marking”, on page 621.
41.3.1 Ethernet MAC (EMAC)
41.3.1.1 EMAC: Possible Event Loss when Reading EMAC_ISR
If an event occurs within the same clock cycle in which the EMAC_ISR is read, the correspond-
ing bit might be cleared even though it has not been read at 1. This might lead to the loss of this
event.
Problem Fix/Workaround
Each time the software reads EMAC_ISR, it has to check the contents of the Transmit Status
Register (EMAC_TSR), the Receive Status Register (EMAC_RSR) and the Network Status
Register (EMAC_NSR), as the possible lost event is still notified in one of these registers.
41.3.1.2 EMAC: Possible Event Loss when Reading the Statistics Register Block
If an event occurs within the same clock cycle during which a statistics register is read, the cor-
responding counter might lose this event. This might lead to the loss of the incrementation of
one for this counter.
Problem Fix/Workaround
None
41.3.2 Peripheral Input/Output (PIO)
41.3.2.1 PIO: Leakage on PB27 - PB30
When PB27, PB28, PB29 or PB30 (the I/O lines multiplexed with the analog inputs) are set as
digital inputs with pull-up disabled, the leakage can be 25 µA in worst case and 90 nA in typical
case per I/O when the I/O is set externally at low level.
Problem Fix/Workaround
Set the I/O to VDDIO by internal or external pull-up.
41.3.2.2 PIO: Electrical Characteristics on NRST, PA0-PA30 and PB0-PB26
When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, the volt-
age of the I/O stabilizes at VPull-up.
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at
3.3 V.
Vpull-up
VPull-up Min VPull-up Max
VDDIO - 0.65 V VDDIO - 0.45 V
I Leakage
Parameter Typ Max
I Leakage at 3,3V 2.5
µA 45 µA