Datasheet

6120F–ATARM–03-Oct-06

AT91SAM7X512/256/128 Preliminary

13.3.3.3 Brownout Reset

When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters

the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are

asserted.

The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset

after a two-cycle resynchronization. An external reset is also triggered.

When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value

0x5, thus indicating that the last reset is a Brownout Reset.

Figure 13-6. Brownout Reset State

SLCK

periph_nreset

proc_nreset

brown_out

or bod_reset

NRST

(nrst_out)

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

MCK

Processor Startup

= 3 cycles

Any

Freq.

RSTTYP

Any

XXX

0x5 = Brownout Reset

Resynch.

2 cycles