Datasheet

557
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
The VLAN tag is inserted at the 13
th
byte of the frame, adding an extra four bytes to the frame. If
the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame. The MAC can
support frame lengths up to 1536 bytes, 18 bytes more than the original Ethernet maximum
frame length of 1518 bytes. This is achieved by setting bit 8 in the network configuration register.
The following bits in the receive buffer descriptor status word give information about VLAN
tagged frames:
• Bit 21 set if receive frame is VLAN tagged (i.e. type id of 0x8100)
• Bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null VID). (If bit 20 is
set bit 21 is set also.)
• Bit 19, 18 and 17 set to priority if bit 21 is set
• Bit 16 set to CFI if bit 21 is set
37.3.11 PHY Maintenance
The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO
interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are config-
ured for the same speed and duplex configuration.
The PHY maintenance register is implemented as a shift register. Writing to the register starts a
shift operation which is signalled as complete when bit two is set in the network status register
(about 2000 MCK cycles later when bit ten is set to zero, and bit eleven is set to one in the net-
work configuration register). An interrupt is generated as this bit is set. During this time, the MSB
of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each
MDC cycle. This causes transmission of a PHY management frame on MDIO.
Reading during the shift operation returns the current contents of the shift register. At the end of
management operation, the bits have shifted back to their original locations. For a read opera-
tion, the data bits are updated with data read from the PHY. It is important to write the correct
values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read
clause 45 PHYs, bits[31:28] should be written as 0x0011. For a description of MDC generation,
see the network configuration register in the ”Network Control Register” on page 564.
37.3.12 Media Independent Interface
The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the
EMAC_USRIO register controls the interface that is selected. When this bit is set, the RMII inter-
face is selected, else the MII interface is selected.
The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in
the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in
Table 37-5.
Table 37-5. Pin Configuration
Pin Name MII RMII
ETXCK_EREFCK ETXCK: Transmit Clock EREFCK: Reference Clock
ECRS ECRS: Carrier Sense
ECOL ECOL: Collision Detect
ERXDV ERXDV: Data Valid ECRSDV: Carrier Sense/Data Valid