Datasheet

504
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
36.6.5.1 Enabling Low-power Mode
A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR
global register. The CAN controller enters Low-power Mode once all pending transmit mes-
sages are sent.
When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register
is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is gener-
ated while SLEEP is set.
The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The
WAKEUP signal is automatically cleared once SLEEP is set.
Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is impor-
tant to note that those messages with higher priority than the last message transmitted can be
received between the LPM command and entry in Low-power Mode.
Once in Low-power Mode, the CAN controller clock can be switched off by programming the
chip’s Power Management Controller (PMC). The CAN controller drains only the static current.
Error counters are disabled while the SLEEP signal is set to one.
Thus, to enter Low-power Mode, the software application must:
– Set LPM field in the CAN_MR register
– Wait for SLEEP signal rising
Now the CAN Controller clock can be disabled. This is done by programming the Power Man-
agement Controller (PMC).
Figure 36-8. Enabling Low-power Mode
36.6.5.2 Disabling Low-power Mode
The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is
done by an external module that may be embedded in the chip. When it is notified of a CAN
bus activity, the software application disables Low-power Mode by programming the CAN
controller.
SLEEP
(CAN_SR)
MRDY
(CAN_MSR1)
LPM
(CAN_MR)
LPEN= 1
CAN BUS
MRDY
(CAN_MSR3)
Mailbox 1
Mailbox 3
Arbitration lost
WAKEUP
(CAN_SR)
0x0CAN_TIM