Datasheet

49
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1
JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per-
formed after JTAGSEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
12.5.4.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains 187 bits that correspond to active pins and associ-
ated control signals.
Each AT91SAM7X input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit
contains data that can be forced on the pad. The INPUT bit facilitates the observability of data
applied to the pad. The CONTROL bit selects the direction of the pad.
Table 12-2. AT91SAM7X JTAG Boundary Scan Register
Bit
Number Pin Name Pin Type
Associated BSR
Cells
187
PA30/IRQ0/PCK2 IN/OUT
INPUT
186 OUTPUT
185 CONTROL
184
PA0/RXD0 IN/OUT
INPUT
183 OUTPUT
182 CONTROL
181
PA1/TXD0 IN/OUT
INPUT
180 OUTPUT
179 CONTROL
178
PA3/RTS0/SPI1_NPCS2 IN/OUT
INPUT
177 OUTPUT
176 CONTROL
175
PA2/SCK0/SPI1_NPCS1 IN/OUT
INPUT
174 OUTPUT
173 CONTROL
172
PA4/CTS0/SPI1_NPCS3 IN/OUT
INPUT
171 OUTPUT
170 CONTROL
169
PA5/RXD1 IN/OUT
INPUT
168 OUTPUT
167 CONTROL
166
PA6/TXD1 IN/OUT
CONTROL
165 INPUT
164 OUTPUT