Datasheet

47
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
12.3.2 Test Environment
Figure 12-3 shows a test environment example. Test vectors are sent and interpreted by the
tester. In this example, the “board in test” is designed using a number of JTAG-compliant
devices. These devices can be connected to form a single scan chain.
Figure 12-3. Application Test Environment Example
12.4 Debug and Test Pin Description
Tester
JTAG
Interface
ICE/JTAG
Connector
AT91SAM7Xxx-based Application Board In Test
AT91SAM7Xxx
Test Adaptor
Chip 2Chip n
Chip 1
Table 12-1. Debug and Test Pin List
Pin Name Function Type Active Level
Reset/Test
NRST Microcontroller Reset Input/Output Low
TST Test Mode Select Input High
ICE and JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
JTAGSEL JTAG Selection Input
Debug Unit
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output