Datasheet

449
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
1. The microcontroller sets the FORCESTALL flag in the UDP_ CSRx endpoint’s register.
2. The host receives the stall packet.
3. The microcontroller is notified that the device has sent the stall by polling the
STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The
microcontroller must clear STALLSENT to clear the interrupt.
When a setup transaction is received after a stall handshake, STALLSENT must be cleared in
order to prevent interrupts due to STALLSENT being set.
Figure 34-12. Stall Handshake (Data IN Transfer)
Figure 34-13. Stall Handshake (Data OUT Transfer)
Data IN Stall PIDPID
USB Bus
Packets
Cleared by Firmware
Set by Firmware
FORCESTALL
STALLSENT
Set by
USB Device
Cleared by Firmware
Interrupt Pending
Data OUT PID
Stall PID
Data OUT
USB Bus
Packets
Cleared by Firmware
Set by Firmware
FORCESTALL
STALLSENT
Set by USB Device
Interrupt Pending