Datasheet

432
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
33.6.10 PWM Channel Duty Cycle Register
Register Name: PWM_
CDTYx
Access Type: Read/Write
Only the first 16 bits (internal channel counter size) are significative.
• CDTY: Channel Duty Cycle
Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
33.6.11 PWM Channel Period Register
Register Name: PWM_CPRDx
Access Type: Read/Write
Only the first 16 bits (internal channel counter size) are significative.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
31 30 29 28 27 26 25 24
CDTY
23 22 21 20 19 18 17 16
CDTY
15 14 13 12 11 10 9 8
CDTY
76543210
CDTY
31 30 29 28 27 26 25 24
CPRD
23 22 21 20 19 18 17 16
CPRD
15 14 13 12 11 10 9 8
CPRD
76543210
CPRD
X CPRD×()
MCK
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