Datasheet

424
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
33.5.3.4 Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end
of the corresponding channel period. The interrupt remains active until a read operation in the
PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A chan-
nel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.