Datasheet

419
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
or
the waveform duty cycle. This channel parameter is defined in the CDTY field of the
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
the waveform polarity. At the beginning of the period, the signal can be at high or low level.
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
the waveform alignment. The output waveform can be left or center aligned. Center aligned
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
Figure 33-4. Non Overlapped Center Aligned Waveforms
(1)
Note: 1. See Figure 33-5 on page 421 for a detailed description of center aligned waveforms.
CRPD DIVA×()
MCK
------------------------------------------
CRPD DIVAB×()
MCK
----------------------------------------------
2 X CPRD××()
MCK
-----------------------------------------
2 CPRD DIVA××()
MCK
----------------------------------------------------
2 CPRD× DIVB×()
MCK
----------------------------------------------------
duty cycle
period 1 fchannel_x_clock CDTY×()
period
--------------------------------------------------------------------------------------------------------=
duty cycle
period 2()1 fchannel_x_clock CDTY×())
period 2()
-----------------------------------------------------------------------------------------------------------------------=
PWM0
PWM1
Period
No overlap