Datasheet

348
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to
unpredictable results.
Figure 31-6. Transmitter Clock Management
31.6.1.3 Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external
clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in
SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently
by the CKI bits in SSC_RCMR.
The receiver can also drive the RK I/O pad continuously or be limited to the actual data trans-
fer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion
(CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK
pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpre-
dictable results.
Figure 31-7. Receiver Clock Management
31.6.1.4 Serial Clock Ratio Considerations
The Transmitter and the Receiver can be programmed to operate with the clock signals pro-
vided on either the TK or RK pins. This allows the SSC to support many slave-mode data
transfers. In this case, the maximum clock speed allowed on the RK pin is:
– Master Clock divided by 2 if Receiver Frame Synchro is input
– Master Clock divided by 3 if Receiver Frame Synchro is output
In addition, the maximum clock speed allowed on the TK pin is:
– Master Clock divided by 6 if Transmit Frame Synchro is input
– Master Clock divided by 2 if Transmit Frame Synchro is output
Receiver Clock
Divider Clock
Transmitter Clock
SSC_TCMR.CKI
SSC_TCMR.CKS
TK
SSC_TCMR.CKO
1
0
TK
Transmitter Clock
Divider Clock
Receiver Clock
SSC_RCMR.CKI
SSC_RCMR.CKS
RK
SSC_RCMR.CKO
1
0
RK