Datasheet

291

6120F–ATARM–03-Oct-06

AT91SAM7X512/256/128 Preliminary

29.6.6 TWI Status Register

Access Type: Read-only

• TXCOMP: Transmission Completed

0 = In master, during the length of the current frame. In slave, from START received to STOP received.

1 = When both holding and shift registers are empty and STOP condition has been sent (in Master), or when MSEN is set

(enable TWI).

• RXRDY: Receive Holding Register Ready

0 = No character has been received since the last TWI_RHR read operation.

1 = A byte has been received in the TWI_RHR since the last read.

• TXRDY: Transmit Holding Register Ready

0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.

1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the

same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).

• NACK: Not Acknowledged

0 = Each data byte has been correctly received by the far-end side TWI slave component.

1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.

31 30 29 28 27 26 25 24

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23 22 21 20 19 18 17 16

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15 14 13 12 11 10 9 8

–––––––NACK

76543210

–––––TXRDYRXRDYTXCOMP