Datasheet

285
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
Figure 29-11. TWI Read in Master Mode
Set TWI clock:
TWI_CWGR = clock
Set the control register:
- Master enable
- Slave disable
TWI_CR = MSEN
Set the Master Mode register:
- Device slave address
- Internal address size
- Transfer direction bit
Read ==> bit MREAD = 0
Internal address size = 0?
Start the transfer
TWI_CR = START
Stop the transfer
TWI_CR = STOP
Read status register
RXRDY = 0?
Data to read?
Read status register
TXCOMP = 0?
END
START
Set the internal address
TWI_IADR = address
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