Datasheet

284
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
29.5.4 Read/Write Flowcharts
The following flowcharts shown in Figure 29-10 and in Figure 29-11 on page 285 give examples
for read and write operations in Master Mode. A polling or interrupt method can be used to check
the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be
configured first.
Figure 29-10. TWI Write in Master Mode
Set TWI clock:
TWI_CWGR = clock
Set the control register:
- Master enable
TWI_CR = MSEN
Set the Master Mode register:
- Device slave address
- Internal address size
- Transfer direction bit
Write ==> bit MREAD = 0
Internal address size = 0?
Load transmit register
TWI_THR = Data to send
Start the transfer
TWI_CR = START
Stop the transfer
TWI_CR = STOP
Read status register
TXRDY = 0?
Data to send?
Read status register
TXCOMP = 0?
END
START
Set theinternal address
TWI_IADR = address
Ye s
TWI_THR = data to send
Ye s
Ye s
Ye s