Datasheet

282
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the
other status bits, an interrupt can be generated if enabled in the interrupt enable register
(TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in the
control register starts the transmission. The data is shifted in the internal shifter and when an
acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see Figure 29-
6 below). The master generates a stop condition to end the transfer.
The read sequence begins by setting the START bit. When the RXRDY bit is set in the status
register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY
bit is reset when reading the TWI_RHR.
The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address).
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a
slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the
other slave address bits in the internal address register (TWI_IADR).
Figure 29-5. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 29-6. Master Write with One Byte Internal Address and Multiple Data Bytes
Figure 29-7. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P
S DADR W A IADR(15:8) A IADR(7:0) A P
DATA A
A IADR(7:0) A P
DATA AS DADR W
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
TWD
TWD
A IADR(7:0) A
DATA AS DADR W
DATA A P
DATA A
TXCOMP
TXRDY
Write THR
Write THR
Write THR Write THR
TWD
S DADR
W
A IADR(23:16) A
IADR(15:8)
A
IADR(7:0) A
S DADR W A IADR(15:8)
A IADR(7:0) A
A
IADR(7:0) A
S DADR W
DATA N P
S DADR R A
S DADR R A DATA N P
S
DADR
R A DATA N P
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address