Datasheet

281
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
29.5 Functional Description
29.5.1 Transfer format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
29-4 on page 281).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
29-3 on page 281).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 29-3. START and STOP Conditions
Figure 29-4. Transfer Format
29.5.2 Modes of Operation
The TWI has two modes of operation:
• Master transmitter mode
• Master receiver mode
The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this
mode, it generates the clock according to the value programmed in the Clock Waveform Gener-
ator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the
interface to be adapted to a wide range of clocks.
29.5.3 Transmitting Data
After the master initiates a Start condition, it sends a 7-bit slave address, configured in the Mas-
ter Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave
address indicates the transfer direction (write or read). If this bit is 0, it indicates a write operation
(transmit operation). If the bit is 1, it indicates a request for data read (receive operation).
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down in
order to generate the acknowledge. The master polls the data line during this clock pulse and
TWD
TWCK
Start Stop
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop