Datasheet

28
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
9.3 Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide:
• the Processor Clock PCK
• the Master Clock MCK
• the USB Clock UDPCK
• all the peripheral clocks, independently controllable
• four programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating fre-
quency of the device.
The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing
reduced power consumption while waiting for an interrupt.
Figure 9-3. Power Management Controller Block Diagram
9.4 Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor
• Individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.)
– Other sources control the peripheral interrupts or external interrupts
– Programmable edge-triggered or level-sensitive internal sources
– Programmable positive/negative edge-triggered or high/low level-sensitive external
sources
• 8-level Priority Controller
– Drives the normal interrupt nIRQ of the processor
– Handles priority of the interrupt sources
MCK
periph_clk[2..18]
int
UDPCK
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,...,/64
PCK
Processor
Clock
Controller
Idle Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
USB Clock Controller
ON/OFF
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
PLLCK
Divider
/1,/2,/4
pck[0..3]