Datasheet

279
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
29. Two-wire Interface (TWI)
29.1 Overview
The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of
one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-ori-
ented transfer format. It can be used with any Atmel two-wire bus Serial EEPROM. The TWI is
programmable as a master with sequential or single-byte access. A configurable baud rate gen-
erator permits the output data rate to be adapted to a wide range of core clock frequencies.
29.2 Block Diagram
Figure 29-1. Block Diagram
29.3 Application Block Diagram
Figure 29-2. Application Block Diagram
APB Bridge
PMC
MCK
Two-wire
Interface
PIO
AIC
TWI
Interrupt
TWCK
TWD
Host with
TWI
Interface
TWD
TWCK
AT24LC16
U1
AT24LC16
U2
LCD Controller
U3
Slave 1 Slave 2 Slave 3
RR
VDD