Datasheet

155
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
23.7.2.2 External Interrupt Level Sensitive Source
Figure 23-7. External Interrupt Level Sensitive Source
23.7.2.3 Internal Interrupt Edge Triggered Source
Figure 23-8. Internal Interrupt Edge Triggered Source
23.7.2.4 Internal Interrupt Level Sensitive Source
Figure 23-9. Internal Interrupt Level Sensitive Source
Maximum IRQ
Latency = 3 Cycles
Maximum FIQ
Latency = 3 cycles
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level)
nIRQ
nFIQ
MCK
nIRQ
Peripheral Interrupt
Becomes Active
Maximum IRQ Latency = 4.5 Cycles
MCK
nIRQ
Maximum IRQ Latency = 3.5 Cycles
Peripheral Interrupt
Becomes Active