Datasheet

142
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
22.4 Peripheral DMA Controller (PDC) User Interface
Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.).
Table 22-1. Peripheral DMA Controller (PDC) Register Mapping
Offset
Register Register Name Read/Write Reset
0x100 Receive Pointer Register PERIPH
(1)
_RPR Read/Write 0x0
0x104 Receive Counter Register PERIPH_RCR Read/Write 0x0
0x108 Transmit Pointer Register PERIPH_TPR Read/Write 0x0
0x10C Transmit Counter Register PERIPH_TCR Read/Write 0x0
0x110 Receive Next Pointer Register PERIPH_RNPR Read/Write 0x0
0x114 Receive Next Counter Register PERIPH_RNCR Read/Write 0x0
0x118 Transmit Next Pointer Register PERIPH_TNPR Read/Write 0x0
0x11C Transmit Next Counter Register PERIPH_TNCR Read/Write 0x0
0x120 PDC Transfer Control Register PERIPH_PTCR Write-only -
0x124 PDC Transfer Status Register PERIPH_PTSR Read-only 0x0