Datasheet

127
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
20.3.2 Entering Serial Programming Mode
The following algorithm puts the device in Serial Programming Mode:
• Apply GND, VDDIO, VDDCORE, VDDFLASH and VDDPLL.
• Apply XIN clock within T
POR_RESET
+ 32(T
SCLK
) if an external clock is available.
•Wait for T
POR_RESET
.
• Reset the TAP controller clocking 5 TCK pulses with TMS set.
• Shift 0x2 into the IR register (IR is 4 bits long, LSB first) without going through the Run-
Test-Idle state.
• Shift 0x2 into the DR register (DR is 4 bits long, LSB first) without going through the Run-
Test-Idle state.
• Shift 0xC into the IR register (IR is 4 bits long, LSB first) without going through the Run-
Test-Idle state.
Note: After reset, the device is clocked by the internal RC oscillator. Before clearing RDY signal, if an
external clock ( > 32 kHz) is connected to XIN, then the device will switch on the external clock.
Else, XIN input is not considered. A higher frequency on XIN speeds up the programmer
handshake.
Test
TST Test Mode Select Input High Must be connected to VDDIO.
PGMEN0 Test Mode Select Input High Must be connected to VDDIO
PGMEN1 Test Mode Select Input High Must be connected to VDDIO
JTAG
TCK JTAG TCK Input - Pulled-up input at reset
TDI JTAG Test Data In Input - Pulled-up input at reset
TDO JTAG Test Data Out Output -
TMS JTAG Test Mode Select Input - Pulled-up input at reset
Table 20-17. Signal Description List (Continued)
Signal Name Function Type
Active
Level Comments
Table 20-18. Reset TAP Controller and Go to Select-DR-Scan
TDI TMS TAP Controller State
X1
X1
X1
X1
X 1 Test-Logic Reset
X 0 Run-Test/Idle
X 1 Select-DR-Scan