Datasheet

118
6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary
20.2.2 Signal Names
Depending on the MODE settings, DATA is latched in different internal registers.
Table 20-1. Signal Description List
Signal Name Function Type
Active
Level Comments
Power
VDDFLASH Flash Power Supply Power
VDDIO I/O Lines Power Supply Power
VDDCORE Core Power Supply Power
VDDPLL PLL Power Supply Power
GND Ground Ground
Clocks
XIN
Main Clock Input.
This input can be tied to GND. In this
case, the device is clocked by the internal
RC oscillator.
Input 32 kHz to 50 MHz
Test
TST Test Mode Select Input High Must be connected to VDDIO
PGMEN0 Test Mode Select Input High Must be connected to VDDIO
PGMEN1 Test Mode Select Input High Must be connected to VDDIO
PIO
PGMNCMD Valid command available Input Low Pulled-up input at reset
PGMRDY
0: Device is busy
1: Device is ready for a new command
Output High Pulled-up input at reset
PGMNOE Output Enable (active high) Input Low Pulled-up input at reset
PGMNVALID
0: DATA[15:0] is in input mode
1: DATA[15:0] is in output mode
Output Low Pulled-up input at reset
PGMM[3:0] Specifies DATA type (See Table 20-2) Input Pulled-up input at reset
PGMD[15:0] Bi-directional data bus Input/Output Pulled-up input at reset
Table 20-2. Mode Coding
MODE[3:0] Symbol Data
0000 CMDE Command Register
0001 ADDR0 Address Register LSBs
0010 ADDR1
0101 DATA Data Register
Default IDLE No register