Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash – 512 Kbytes (AT91SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (AT91SAM7X128) Organized in 512 Pa
• Two Parallel Input/Output Controllers (PIO) • • • • • • • • • • • • • • • • • 2 – Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output Thirteen Peripheral DMA Controller (PDC) Channels One USB 2.
AT91SAM7X512/256/128 Preliminary 1. Description Atmel's AT91SAM7X512/256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 512/256/128 Kbyte high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC and a CAN controller. A complete set of system functions minimizes the number of external components.
2. AT91SAM7X512/256/128 Block Diagram Figure 2-1. AT91SAM7X512/256/128 Block Diagram TDI TDO TMS TCK ICE JTAG SCAN ARM7TDMI Processor JTAGSEL 1.
AT91SAM7X512/256/128 Preliminary 3. Signal Description Table 3-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDIN Voltage Regulator and ADC Power Supply Input Power 3V to 3.6V VDDOUT Voltage Regulator Output Power 1.85V VDDFLASH Flash and USB Power Supply Power 3V to 3.6V VDDIO I/O Lines Power Supply Power 3V to 3.6V VDDCORE Core Power Supply Power 1.65V to 1.95V VDDPLL PLL Power 1.65V to 1.
Table 3-1.
AT91SAM7X512/256/128 Preliminary Table 3-1.
4. Package The AT91SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHScompliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical description is given in the Mechanical Characteristics section. Figure 4-1.
AT91SAM7X512/256/128 Preliminary 4.2 100-lead LQFP Pinout Table 4-1.
4.3 100-ball TFBGA Package Outline Figure 4-2 shows the orientation of the 100-ball TFBGA package. A detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-2. 100-ball TFBGA Package Outline (Top View) TOP VIEW 10 9 8 7 6 5 4 3 2 1 A BALL A1 4.
AT91SAM7X512/256/128 Preliminary 5. Power Considerations 5.1 Power Supplies The AT91SAM7X512/256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 5.4 Typical Powering Schematics The AT91SAM7X512/256/128 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL.
AT91SAM7X512/256/128 Preliminary 6. I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. 6.
tor from the I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset. 6.6 I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA.
AT91SAM7X512/256/128 Preliminary 7. Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs at up to 55 MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM high-performance 32-bit instruction set – Thumb high code density 16-bit instruction set • Three-stage pipeline architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 7.
• Embedded Flash Controller – Embedded Flash interface, up to three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation 7.
AT91SAM7X512/256/128 Preliminary 8. Memories 8.
Figure 8-1.
AT91SAM7X512/256/128 Preliminary 8.4 8.4.1 Memory Mapping Internal SRAM • The AT91SAM7X512 embeds a high-speed 128 Kbyte SRAM bank. • The AT91SAM7X256 embeds a high-speed 64 Kbyte SRAM bank. • The AT91SAM7X128 embeds a high-speed 32 Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.4.2 Internal ROM The AT91SAM7X512/256/128 embeds an Internal ROM.
Figure 8-3. Internal Memory Mapping with GPNVM Bit 2 = 1 0x0000 0000 0x000F FFFF Flash Before Remap SRAM After Remap 1 M Bytes 0x0010 0000 Internal FLASH 1 M Bytes Internal SRAM 1 M Bytes Internal ROM 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 0x003F FFFF 0x0040 0000 Undefined Areas (Abort) 252 M Bytes 0x0FFF FFFF 8.5 Embedded Flash 8.5.1 Flash Overview • The Flash of the AT91SAM7X512 is organized in two banks (dual plane) of 1024 pages of 256 bytes.
AT91SAM7X512/256/128 Preliminary plane may be performed even while program or erase functions are being executed in the other memory plane. One EFC is embedded in the AT91SAM7X256/128 to control the single plane of 256/128 KBytes. 8.5.3 8.5.3.1 Lock Regions AT91SAM7X512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands.
Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted.
AT91SAM7X512/256/128 Preliminary • Communication via the USB Device Port is limited to an 18.432 MHz crystal. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped at address 0x0 when the GPNVM Bit 2 is set to 0. When GPNVM bit 2 is set to 1, the device boots from the Flash. When GPNVM bit 2 is set to 0, the device boots from ROM (SAM-BA).
9. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 9-1 on page 25 shows the System Controller Block Diagram. Figure 8-1 on page 18 shows the mapping of the User Interface of the System Controller peripherals.
AT91SAM7X512/256/128 Preliminary Figure 9-1. System Controller Block Diagram System Controller jtag_nreset Boundary Scan TAP Controller nirq irq0-irq1 Advanced Interrupt Controller fiq periph_irq[2..
9.1 Reset Controller • Based on one power-on reset cell and one brownout detector • Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset • Controls the internal resets and the NRST pin output • Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. 9.1.1 Brownout Detector and Power-on Reset The AT91SAM7X512/256/128 embeds one brownout detection circuit and a power-on reset cell.
AT91SAM7X512/256/128 Preliminary 9.2 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2.
9.3 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • four programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device.
AT91SAM7X512/256/128 Preliminary – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes interrupt service routine branch and execution – One 32-bit vector register per interrupt source – Interrupt vector register reads the corresponding current interrupt vector • Protect Mode – Easy debugging by preventing automatic operations • Fast Forcing – Permits redirecting any interrupt source on the fast interrupt • General Interrupt Mask – Provides processor sy
9.8 Real-time Timer • 32-bit free-running counter with alarm running on prescaled SLCK • Programmable 16-bit prescaler for SLCK accuracy compensation 9.
AT91SAM7X512/256/128 Preliminary 10. Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 Mbytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in Figure 8-1 on page 18. 10.2 Peripheral Identifiers The AT91SAM7X512/256/128 embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the AT91SAM7X512/256/128.
10.3 Peripheral Multiplexing on PIO Lines The AT91SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller.
AT91SAM7X512/256/128 Preliminary 10.4 PIO Controller A Multiplexing Table 10-2.
10.5 PIO Controller B Multiplexing Table 10-3.
AT91SAM7X512/256/128 Preliminary 10.6 Ethernet MAC • DMA Master on Receive and Transmit Channels • Compatible with IEEE Standard 802.
• One, two or three bytes for slave address • Sequential read/write operations 10.9 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.
AT91SAM7X512/256/128 Preliminary – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs • Five internal clock inputs, as defined in Table 10-4 Table 10-4.
10.14 CAN Controller • Fully compliant with CAN 2.0A and 2.0B • Bit rates up to 1Mbit/s • Eight object oriented mailboxes each with the following properties: – CAN Specification 2.0 Part A or 2.
AT91SAM7X512/256/128 Preliminary 11. ARM7TDMI Processor Overview 11.1 Overview The ARM7TDMI core executes both the 32-bit ARM® and 16-bit Thumb® instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages.
11.2 ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) 11.2.1 Instruction Type Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). 11.2.2 Data Type ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries.
AT91SAM7X512/256/128 Preliminary Table 11-1.
A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 11.2.4.2 Status Registers All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR).
AT91SAM7X512/256/128 Preliminary Table 11-2. 11.2.
Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 11-3 gives the Thumb instruction mnemonic list. Table 11-3.
AT91SAM7X512/256/128 Preliminary 12. Debug and Test Features 12.1 Description The AT91SAM7X Series features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM.
12.3 12.3.1 Application Examples Debug Environment Figure 12-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2.
AT91SAM7X512/256/128 Preliminary 12.3.2 Test Environment Figure 12-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n AT91SAM7Xxx Chip 2 Chip 1 AT91SAM7Xxx-based Application Board In Test 12.
12.5 12.5.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 12.5.2 EmbeddedICE™ (Embedded In-circuit Emulator) The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port. The internal state of the ARM7TDMI is examined through an ICE/JTAG port.
AT91SAM7X512/256/128 Preliminary with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 12.5.4.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 187 bits that correspond to active pins and associated control signals.
Table 12-2.
AT91SAM7X512/256/128 Preliminary Table 12-2.
Table 12-2.
AT91SAM7X512/256/128 Preliminary Table 12-2.
Table 12-2.
AT91SAM7X512/256/128 Preliminary 12.5.5 ID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 MANUFACTURER IDENTITY 3 2 1 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number AT91SAM7X512: 0x5B18 AT91SAM7X256: 0x5B10 AT91SAM7X128: 0x5B0F • MANUFACTURER IDENTITY[11:1] Set to 0x01F.
AT91SAM7X512/256/128 Preliminary 6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary 13. Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. A brownout detection is also available to prevent the processor from falling into an unpredictable state. 13.2 Block Diagram Figure 13-1.
13.3 Functional Description The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action.
AT91SAM7X512/256/128 Preliminary 13.3.1.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds.
13.3.3 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 13.3.3.1 Power-up Reset When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock.
AT91SAM7X512/256/128 Preliminary 13.3.3.2 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup.
13.3.3.3 Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered.
AT91SAM7X512/256/128 Preliminary 13.3.3.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command.
13.3.3.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. • If WDRPROC = 1, only the processor reset is asserted.
AT91SAM7X512/256/128 Preliminary 13.3.4 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Power-up Reset • Brownout Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed below: • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated.
Figure 13-9.
AT91SAM7X512/256/128 Preliminary 13.4 Reset Controller (RSTC) User Interface Table 13-1.
13.4.1 Reset Controller Control Register Register Name: RSTC_CR Access Type: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect.
AT91SAM7X512/256/128 Preliminary 13.4.2 Reset Controller Status Register Register Name: RSTC_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 BODSTS 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR.
13.4.3 Reset Controller Mode Register Register Name: RSTC_MR Access Type: Read/Write 31 30 29 28 27 26 25 24 17 – 16 BODIEN 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 – 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.
AT91SAM7X512/256/128 Preliminary 14. Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value. 14.2 Block Diagram Figure 14-1.
The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set.
AT91SAM7X512/256/128 Preliminary 14.4 Real-time Timer (RTT) User Interface Table 14-1.
14.4.1 Real-time Timer Mode Register Register Name: RTT_MR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer.
AT91SAM7X512/256/128 Preliminary 14.4.2 Real-time Timer Alarm Register Register Name: RTT_AR Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 14.4.
14.4.4 Real-time Timer Status Register Register Name: RTT_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR.
AT91SAM7X512/256/128 Preliminary 15. Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1.
15.3 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR).
AT91SAM7X512/256/128 Preliminary Figure 15-2.
15.4 Periodic Interval Timer (PIT) User Interface Table 15-1.
AT91SAM7X512/256/128 Preliminary 15.4.1 Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 PITIEN 24 PITEN 23 – 22 – 21 – 20 – 19 18 17 16 15 14 13 12 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
15.4.3 Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 25 24 17 16 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer.
AT91SAM7X512/256/128 Preliminary 16. Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.2 Block Diagram Figure 16-1.
16.3 Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).
AT91SAM7X512/256/128 Preliminary Figure 16-2.
16.4 Watchdog Timer (WDT) User Interface Table 16-1. Watchdog Timer (WDT) Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 16.4.
AT91SAM7X512/256/128 Preliminary 16.4.2 Watchdog Timer Mode Register Register Name: WDT_MR Access Type: Read/Write Once 31 – 30 – 29 WDIDLEHLT 28 WDDBGHLT 27 26 23 22 21 20 19 18 11 10 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter.
16.4.3 Watchdog Timer Status Register Register Name: WDT_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
AT91SAM7X512/256/128 Preliminary 17. Voltage Regulator Mode Controller (VREG) 17.1 Overview The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset. This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake up the Voltage Regulator in Normal Mode.
17.2 Voltage Regulator Power Controller (VREG) User Interface Table 17-1. Voltage Regulator Power Controller Register Mapping Offset Register Name 0x60 Voltage Regulator Mode Register VREG_MR 17.2.
AT91SAM7X512/256/128 Preliminary 18. Memory Controller (MC) 18.1 Overview The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a bus arbiter, an address decoder, an abort status, a misalignment detector and an Embedded Flash Controller. 18.2 Block Diagram Figure 18-1.
18.3 Functional Description The Memory Controller handles the internal ASB bus and arbitrates the accesses of up to three masters. It is made up of: • A bus arbiter • An address decoder • An abort status • A misalignment detector • An Embedded Flash Controller The MC handles only little-endian mode accesses. The masters work in little-endian mode only. 18.3.1 Bus Arbiter The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the three masters.
AT91SAM7X512/256/128 Preliminary 18.3.2.1 Internal Memory Mapping Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories. The allocated memories are accessed all along the 1-Mbyte address space and so are repeated n times within this address space, n equaling 1M bytes divided by the size of the memory.
18.3.4 Abort Status There are two reasons for an abort to occur: • access to an undefined address • an access to a misaligned address. When an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access. However, only the ARM7TDMI can take an abort signal into account, and only under the condition that it was generating an access. The Peripheral DMA Controller and the EMAC do not handle the abort input signal.
AT91SAM7X512/256/128 Preliminary As the requested address is saved in the Abort Status Register and the address of the instruction generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified.
18.4 Memory Controller (MC) User Interface Base Address: 0xFFFFFF00 Table 18-1. Memory Controller (MC) Register Mapping Offset Register Name Access 0x00 MC Remap Control Register MC_RCR Write-only 0x04 MC Abort Status Register MC_ASR Read-only 0x0 0x08 MC Abort Address Status Register MC_AASR Read-only 0x0 0x10-0x5C Reserved 0x60 EFC0 Configuration Registers 0x70 EFC1(1) Configuration Registers Note: 96 Reset State See the Embedded Flash Controller Section 1.
AT91SAM7X512/256/128 Preliminary 18.4.1 MC Remap Control Register Register Name: MC_RCR Access Type: Write-only Offset: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – RCB • RCB: Remap Command Bit 0: No effect.
18.4.
AT91SAM7X512/256/128 Preliminary • MST_PDC: PDC Abort Source 0: The last aborted access was not due to the PDC. 1: The last aborted access was due to the PDC. • MST_ARM: ARM Abort Source 0: The last aborted access was not due to the ARM. 1: The last aborted access was due to the ARM. • SVMST_EMAC: Saved EMAC Abort Source 0: No abort due to the EMAC occurred since the last read of MC_ASR or it is notified in the bit MST_EMAC. 1: At least one abort due to the EMAC occurred since the last read of MC_ASR.
18.4.3 MC Abort Address Status Register Register Name: MC_AASR Access Type: Read-only Reset Value: 0x0 Offset: 0x08 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ABTADD 23 22 21 20 ABTADD 15 14 13 12 ABTADD 7 6 5 4 ABTADD • ABTADD: Abort Address This field contains the address of the last aborted access.
AT91SAM7X512/256/128 Preliminary 19. Embedded Flash Controller (EFC) 19.1 Overview The Embedded Flash Controller (EFC ) is a part of the Memory Controller and ensures the interface of the Flash block with the 32-bit internal bus. It increases performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages the programming, erasing, locking and unlocking sequences using a full set of commands. The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1.
Figure 19-1. Embedded Flash Memory Mapping Page 0 Flash Memory Start Address Lock Region 0 Lock Bit 0 Lock Region 1 Lock Bit 1 Lock Region (n-1) Lock Bit n-1 Page (m-1) Page ( (n-1)*m ) 32-bit wide Page (n*m-1) 19.2.2 Read Operations An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added in order to start access at following address during the second read, thus increasing performance when the processor is running in Thumb mode (16-bit instruction set).
AT91SAM7X512/256/128 Preliminary Figure 19-2.
Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3 3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles 3 Wait State Cycles Master Clock ARM Request (16-bit) Code Fetch @2 @Byte 0 Flash Access Bytes 0-3 Buffer (32 bits) Data To ARM Note: 19.2.
AT91SAM7X512/256/128 Preliminary To run one of these commands, the field FCMD of the MC_FCR register has to be written with the command number. As soon as the MC_FCR register is written, the FRDY flag is automatically cleared. Once the current command is achieved, then the FRDY flag is automatically set. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.
Figure 19-5.
AT91SAM7X512/256/128 Preliminary Figure 19-6. Example of Partial Page Programming: 32 bits wide 32 bits wide 16 words 16 words FF FF FF FF FF FF FF FF FF FF 16 words FF FF FF 16 words FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... FF FF FF FF FF CA FE FF FF CA CA FE FE FF FF ... FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ... FF FF FF FF FF FF FF FF FF FF FF FF FF ... Step 1. Erase All Flash Page 7 erased ... ... ... ...
Erase All operation is allowed only if there are no lock bits set. Thus, if at least one lock region is locked, the bit LOCKE in MC_FSR rises and the command is cancelled. If the bit LOCKE has been written at 1 in MC_FMR, the interrupt line rises. When programming is complete, the bit FRDY bit in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.
AT91SAM7X512/256/128 Preliminary 19.2.4.4 General-purpose NVM Bits General-purpose NVM bits do not interfere with the embedded Flash memory plane. (Does not apply to EFC1 on the AT91SAM7X512.) These general-purpose bits are dedicated to protect other parts of the product. They can be set (activated) or cleared individually. Refer to the product definition section for the general-purpose NVM bit action.
• When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated. When the security bit is active, the SECURITY bit in the MC_FSR is set.
AT91SAM7X512/256/128 Preliminary 19.3 Embedded Flash Controller (EFC ) User Interface The User Interface of the EFC is integrated within the Memory Controller with Base Address: 0xFFFF FF00. The AT91SAM7X512 is equipped with two EFCs, EFC0 and EFC1, as described in the Register Mapping tables and Register descriptions that follow. Table 19-3.
19.3.1 MC Flash Mode Register Register Name: MC_FMR Access Type: Read/Write Offset: (EFC0) 0x60 Offset: (EFC1) 0x70 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 FMCN 15 – 14 – 13 – 12 – 11 – 10 – 9 7 NEBP 6 – 5 – 4 – 3 PROGE 2 LOCKE 1 – 8 FWS 0 FRDY • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt. 1: Flash Ready generates an interrupt.
AT91SAM7X512/256/128 Preliminary • FMCN: Flash Microsecond Cycle Number Before writing Non Volatile Memory bits (Lock bits, General Purpose NVM bit and Security bits), this field must be set to the number of Master Clock cycles in one microsecond. When writing the rest of the Flash, this field defines the number of Master Clock cycles in 1.5 microseconds. This number must be rounded up. Warning: The value 0 is only allowed for a master clock period superior to 30 microseconds.
19.3.2 MC Flash Command Register Register Name: MC_FCR Access Type: Write-only Offset: (EFC0) 0x64 Offset: (EFC1) 0x74 31 30 29 28 27 26 25 24 19 – 18 – 17 16 11 10 9 8 3 2 1 0 KEY 23 – 22 – 21 – 20 – 15 14 13 12 PAGEN PAGEN 7 – 6 – 5 – 4 – FCMD • FCMD: Flash Command This field defines the Flash commands: FCMD 0000 No command. Does not raise the Programming Error Status flag in the Flash Status Register MC_FSR.
AT91SAM7X512/256/128 Preliminary • PAGEN: Page Number Command PAGEN Description Write Page Command PAGEN defines the page number to be written. Write Page and Lock Command PAGEN defines the page number to be written and its associated lock region. Erase All Command This field is meaningless Set/Clear Lock Bit Command PAGEN defines one page number of the lock region to be locked or unlocked. Set/Clear General Purpose NVM Bit Command PAGEN defines the general-purpose bit number.
19.3.
AT91SAM7X512/256/128 Preliminary 20. Fast Flash Programming Interface (FFPI) 20.1 Description The Fast Flash Programming Interface provides two solutions - parallel or serial - for high-volume programming using a standard gang programmer. The parallel interface is fully handshaked and the device is considered to be a standard EEPROM. Additionally, the parallel protocol offers an optimized access to all the embedded Flash functionalities. The serial interface uses the standard IEEE 1149.1 JTAG protocol.
Table 20-1. Signal Name Signal Description List Function Active Level Type Comments Power VDDFLASH Flash Power Supply Power VDDIO I/O Lines Power Supply Power VDDCORE Core Power Supply Power VDDPLL PLL Power Supply Power GND Ground Ground Clocks Main Clock Input. This input can be tied to GND. In this case, the device is clocked by the internal RC oscillator.
AT91SAM7X512/256/128 Preliminary When MODE is equal to CMDE, then a new command (strobed on DATA[15:0] signals) is stored in the command register. Table 20-3.
Figure 20-2. Parallel Programming Timing, Write Sequence NCMD 2 4 3 RDY 5 NOE NVALID DATA[15:0] 1 MODE[3:0] Table 20-4.
AT91SAM7X512/256/128 Preliminary Table 20-5. Read Handshake Step Programmer Action Device Action DATA I/O 1 Sets MODE and DATA signals Waits for NCMD low Input 2 Clears NCMD signal Latch MODE and DATA Input 3 Waits for RDY low Clears RDY signal Input 4 Sets DATA signal in tristate Waits for NOE Low Input 5 Clears NOE signal 6 Waits for NVALID low Tristate 7 Sets DATA bus in output mode and outputs the flash contents.
Table 20-6. 20.2.5.2 Read Command (Continued) Step Handshake Sequence MODE[3:0] DATA[15:0] n+3 Write handshaking ADDR3 32-bit Flash Address Last Byte n+4 Read handshaking DATA *Memory Address++ n+5 Read handshaking DATA *Memory Address++ ... ... ... ... Flash Write Command This command is used to write the Flash contents. The Flash memory plane is organized into several pages. Data to be written are stored in a load buffer that corresponds to a Flash memory page.
AT91SAM7X512/256/128 Preliminary The Flash command Erase Page and Write (EWP) is equivalent to the Flash Write Command. However, before programming the load buffer, the page is erased. The Flash command Erase Page and Write the Lock (EWPL) combines EWP and WPL commands. 20.2.5.3 Flash Full Erase Command This command is used to erase the Flash memory planes. All lock regions must be unlocked before the Full Erase command by using the CLB command.
In the same way, the Clear Fuse command (CFB) is used to clear general-purpose NVM bits. All the general-purpose NVM bits are also cleared by the EA command. The general-purpose NVM bit is deactivated when the corresponding bit in the pattern value is set to 1. Table 20-11.
AT91SAM7X512/256/128 Preliminary The Memory Write command (WRAM) is optimized for consecutive writes. Write handshaking can be chained; an internal address buffer is automatically increased. Table 20-15. Write Command 20.2.5.
20.3 Serial Fast Flash Programming The Serial Fast Flash programming interface is based on IEEE Std. 1149.1 “Standard Test Access Port and Boundary-Scan Architecture”. Refer to this standard for an explanation of terms used in this chapter and for a description of the TAP controller states. In this mode, data read/written from/to the embedded Flash of the device are transmitted through the JTAG interface of the device. 20.3.1 Device Configuration Figure 20-4.
AT91SAM7X512/256/128 Preliminary Table 20-17. Signal Description List (Continued) Signal Name Function Type Active Level Comments Test TST Test Mode Select Input High Must be connected to VDDIO.
20.3.3 Read/Write Handshake The read/write handshake is done by carrying out read/write operations on two registers of the device that are accessible through the JTAG: • Debug Comms Control Register: DCCR • Debug Comms Data Register: DCDR Access to these registers is done through the TAP 38-bit DR register comprising a 32-bit data field, a 5-bit address field and a read/write bit.
AT91SAM7X512/256/128 Preliminary 20.3.4.1 Flash Read Command This command is used to read the Flash contents. The memory map is accessible through this command. Memory is seen as an array of words (32-bit wide). The read command can start at any valid address in the memory plane. This address must be word-aligned. The address is automatically incremented. Table 20-19. Read Command 20.3.4.
20.3.4.3 Flash Full Erase Command This command is used to erase the Flash memory planes. All lock bits must be deactivated before using the Full Erase command. This can be done by using the CLB command. Table 20-21. Full Erase Command 20.3.4.4 Read/Write DR Data Write EA Flash Lock Commands Lock bits can be set using WPL or EWPL commands. They can also be set by using the Set Lock command (SLB). With this command, several lock bits can be activated at the same time.
AT91SAM7X512/256/128 Preliminary GP NVM bits can be read using Get Fuse Bit command (GFB). When a bit set in the Bit Mask is returned, then the corresponding fuse bit is set. Table 20-25. Get General-purpose NVM Bit Command 20.3.4.6 Read/Write DR Data Write GFB Read Bit Mask Flash Security Bit Command Security bits can be set using Set Security Bit command (SSE). Once the security bit is active, the Fast Flash programming is disabled. No other command can be run.
20.3.4.9 Get Version Command The Get Version (GVE) command retrieves the version of the FFPI interface. Table 20-29.
AT91SAM7X512/256/128 Preliminary 21. AT91SAM Boot Program 21.1 Overview The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. SAM-BA™ Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port. 21.2 Flow Diagram The Boot Program implements the algorithm in Figure 21-1. Figure 21-1.
21.4 SAM-BA Boot The SAM-BA boot principle is to: – Check if USB Device enumeration has occurred – Check if the AutoBaudrate sequence has succeeded (see Figure 21-2) Figure 21-2.
AT91SAM7X512/256/128 Preliminary – Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in Table 21-1. Table 21-1.
binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 21.4.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission.
AT91SAM7X512/256/128 Preliminary The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys.
21.5 Hardware and Software Constraints • SAM-BA boot copies itself in the SRAM and uses a block of internal SRAM for variables and stacks. The remaining available size for the user code is 122880 bytes forAT91SAM7x512, 57344 bytes for AT91SAM7X256 and 24576 bytes for AT91SAM7X128. • USB requirements: – pull-up on DDP – 18.432 MHz Quartz Table 21-4.
AT91SAM7X512/256/128 Preliminary 22. Peripheral DMA Controller (PDC) 22.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor intervention and removes the processor interrupt-handling overhead.
22.3 22.3.1 Functional Description Configuration The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to. Per peripheral, it contains four 32-bit Pointer Registers (RPR, RNPR, TPR, and TNPR) and four 16-bit Counter Registers (RCR, RNCR, TCR, and TNCR).
AT91SAM7X512/256/128 Preliminary If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value. Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to re-enable the triggers.
22.4 Peripheral DMA Controller (PDC) User Interface Table 22-1.
AT91SAM7X512/256/128 Preliminary 22.4.1 PDC Receive Pointer Register Register Name: Access Type: 31 PERIPH_RPR Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR • RXPTR: Receive Pointer Address Address of the next receive transfer. 22.4.
22.4.3 PDC Transmit Pointer Register Register Name: Access Type: 31 PERIPH_TPR Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR • TXPTR: Transmit Pointer Address Address of the transmit buffer. 22.4.
AT91SAM7X512/256/128 Preliminary 22.4.5 PDC Receive Next Pointer Register Register Name: Access Type: 31 PERIPH_RNPR Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR • RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when the current buffer is full. 22.4.
22.4.7 PDC Transmit Next Pointer Register Register Name: Access Type: 31 PERIPH_TNPR Read/Write 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR • TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer is empty. 22.4.
AT91SAM7X512/256/128 Preliminary 22.4.9 PDC Transfer Control Register Register Name: Access Type: PERIPH_PTCR Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – TXTDIS TXTEN 7 6 5 4 3 2 1 0 – – – – – – RXTDIS RXTEN • RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables the receiver PDC transfer requests if RXTDIS is not set.
22.4.10 PDC Transfer Status Register Register Name: Access Type: PERIPH_PTSR Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – TXTEN 7 6 5 4 3 2 1 0 – – – – – – – RXTEN • RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. 1 = Receiver PDC transfer requests are enabled.
AT91SAM7X512/256/128 Preliminary 23. Advanced Interrupt Controller (AIC) 23.1 Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
23.3 Application Block Diagram Figure 23-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller External Peripherals (External Interrupts) Embedded Peripherals 23.4 AIC Detailed Block Diagram Figure 23-3.
AT91SAM7X512/256/128 Preliminary 23.6 23.6.1 Product Dependencies I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path. 23.6.2 Power Management The Advanced Interrupt Controller is continuously clocked.
23.7 Functional Description 23.7.1 23.7.1.1 Interrupt Source Control Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode.
AT91SAM7X512/256/128 Preliminary Each status referred to above can be used to optimize the interrupt handling of the systems. 23.7.1.5 Internal Interrupt Source Input Stage Figure 23-4. Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Edge AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR 23.7.1.6 External Interrupt Source Input Stage Figure 23-5.
23.7.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. • Occurrence, either at the processor level or at the AIC level. • The execution time of the instruction in progress when the interrupt occurs. • The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations.
AT91SAM7X512/256/128 Preliminary 23.7.2.2 External Interrupt Level Sensitive Source Figure 23-7. External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles 23.7.2.3 Internal Interrupt Edge Triggered Source Figure 23-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active 23.7.2.
23.7.3 23.7.3.1 Normal Interrupt Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest.
AT91SAM7X512/256/128 Preliminary LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt.
5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing reassertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1.
AT91SAM7X512/256/128 Preliminary 23.7.4 23.7.4.1 Fast Interrupt Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. 23.7.4.2 Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller.
3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 5.
AT91SAM7X512/256/128 Preliminary clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented.
23.7.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR.
AT91SAM7X512/256/128 Preliminary • An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) • An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending.
23.8 Advanced Interrupt Controller (AIC) User Interface 23.8.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only an ± 4-Kbyte offset. 23.8.2 Register Mapping Table 23-2.
AT91SAM7X512/256/128 Preliminary 23.8.3 AIC Source Mode Register Register Name: AIC_SMR0..AIC_SMR31 Access Type: Read/Write Reset Value: 0x0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – SRCTYPE PRIOR • PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0).
23.8.4 AIC Source Vector Register Register Name: AIC_SVR0..AIC_SVR31 Access Type: Read/Write Reset Value: 0x0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. 23.8.
AT91SAM7X512/256/128 Preliminary 23.8.6 AIC FIQ Vector Register Register Name: AIC_FVR Access Type: Read-only Reset Value: 0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. 23.8.
23.8.
AT91SAM7X512/256/128 Preliminary 23.8.10 AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read-only Reset Value: 0 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NIFQ • NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated.
23.8.12 AIC Interrupt Disable Command Register Register Name: AIC_IDCR Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect.
AT91SAM7X512/256/128 Preliminary 23.8.14 AIC Interrupt Set Command Register Register Name: AIC_ISCR Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ • FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect.
23.8.16 AIC Spurious Interrupt Vector Register Register Name: AIC_SPU Access Type: Read/Write Reset Value: 0 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIQV 23 22 21 20 SIQV 15 14 13 12 SIQV 7 6 5 4 SIQV • SIQV: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. 23.8.
AT91SAM7X512/256/128 Preliminary 23.8.18 AIC Fast Forcing Enable Register Register Name: AIC_FFER Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – • SYS, PID2-PID31: Fast Forcing Enable 0 = No effect.
23.8.
AT91SAM7X512/256/128 Preliminary 24. Clock Generator 24.1 Overview The Clock Generator is made up of 1 PLL, a Main Oscillator, as well as an RC Oscillator. It provides the following clocks: • SLCK, the Slow Clock, which is the only permanent clock within the system • MAINCK is the output of the Main Oscillator • PLLCK is the output of the Divider and PLL block The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 25.9.
Figure 24-2. Typical Crystal Connection XIN XOUT GND 1K CL1 CL2 24.3.2 Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the frequency rises. 24.3.3 Main Oscillator Control To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected.
AT91SAM7X512/256/128 Preliminary 24.3.5 24.4 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly.
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
AT91SAM7X512/256/128 Preliminary 25. Power Management Controller (PMC) 25.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks: • MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device.
25.3 Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be enabled and disabled by writing the System Clock Enable (PMC_SCER) and System Clock Disable Registers (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR). The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt.
AT91SAM7X512/256/128 Preliminary The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 25.6 Programmable Clock Output Controller The PMC controls 4 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers.
3. Setting PLL and divider: All parameters needed to configure PLL and the divider are located in the CKGR_PLLR register. The DIV field is used to control divider itself. A value between 0 and 255 can be programmed. Divider output is divider input divided by DIV parameter. By default DIV parameter is set to 0 which means that divider is turned off. The OUT field is used to select the PLL B output frequency range. The MUL field is the PLL multiplier factor.
AT91SAM7X512/256/128 Preliminary • If a new value for CSS field corresponds to PLL Clock, – Program the PRES field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. – Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register. • If a new value for CSS field corresponds to Main Clock or Slow Clock, – Program the CSS field in the PMC_MCKR register. – Wait for the MCKRDY bit to be set in the PMC_SR register.
divided by PRES parameter. By default, the PRES parameter is set to 1 which means that master clock is equal to slow clock. Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register.
AT91SAM7X512/256/128 Preliminary 25.8 25.8.1 Clock Switching Details Master Clock Switching Timings Table 25-1 gives the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 25-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock – 4 x SLCK + 2.
Figure 25-4. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR Figure 25-5.
AT91SAM7X512/256/128 Preliminary Figure 25-6.
25.9 Power Management Controller (PMC) User Interface Table 25-2.
AT91SAM7X512/256/128 Preliminary 25.9.1 PMC System Clock Enable Register Register Name: PMC_SCER Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP – – – – – – PCK • PCK: Processor Clock Enable 0 = No effect. 1 = Enables the Processor clock. • UDP: USB Device Port Clock Enable 0 = No effect.
25.9.2 PMC System Clock Disable Register Register Name: PMC_SCDR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP – – – – – – PCK • PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode. • UDP: USB Device Port Clock Disable 0 = No effect.
AT91SAM7X512/256/128 Preliminary 25.9.3 PMC System Clock Status Register Register Name: PMC_SCSR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCK3 PCK2 PCK1 PCK0 7 6 5 4 3 2 1 0 UDP – – – – – – PCK • PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled.
25.9.4 PMC Peripheral Clock Enable Register Register Name: PMC_PCER Access Type: Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 - - • PIDx: Peripheral Clock x Enable 0 = No effect.
AT91SAM7X512/256/128 Preliminary 25.9.
25.9.7 PMC Clock Generator Main Oscillator Register Register Name: CKGR_MOR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 OSCBYPASS 0 MOSCEN OSCOUNT 7 – 6 – 5 – 4 – • MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Oscillator is disabled. 1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0.
AT91SAM7X512/256/128 Preliminary 25.9.8 PMC Clock Generator Main Clock Frequency Register Register Name: CKGR_MCFR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled.
25.9.9 PMC Clock Generator PLL Register Register Name: CKGR_PLLR Access Type: Read/Write 31 – 30 – 29 23 22 21 28 27 – 26 25 MUL 24 20 19 18 17 16 11 10 9 8 2 1 0 USBDIV MUL 15 14 13 12 OUT 7 PLLCOUNT 6 5 4 3 DIV Possible limitations on PLL input frequencies and multiplier factors should be checked before using the PMC. • DIV: Divider DIV Divider Selected 0 Divider output is 0 1 Divider is bypassed 2 - 255 Divider output is the selected clock divided by DIV.
AT91SAM7X512/256/128 Preliminary 25.9.10 PMC Master Clock Register Register Name: PMC_MCKR Access Type: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – – – 4 3 2 7 6 5 – – – 8 – 1 PRES 0 CSS • CSS: Master Clock Selection CSS Clock Source Selection 0 0 Slow Clock is selected 0 1 Main Clock is selected 1 0 Reserved 1 1 PLL Clock is selected.
25.9.
AT91SAM7X512/256/128 Preliminary 25.9.
25.9.
AT91SAM7X512/256/128 Preliminary 25.9.14 PMC Status Register Register Name: PMC_SR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – PCKRDY3 PCKRDY2 PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 – – – – MCKRDY LOCK – MOSCS • MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized.
25.9.
AT91SAM7X512/256/128 Preliminary 26. Debug Unit (DBGU) 26.1 Overview The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications.
26.2 Block Diagram Figure 26-1. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral DMA Controller APB Debug Unit DTXD Transmit Power Management Controller MCK Parallel Input/ Output Baud Rate Generator Receive DRXD COMMRX R ARM Processor COMMTX DCC Handler Chip ID nTRST ICE Access Handler Interrupt Control dbgu_irq Power-on Reset force_ntrst Table 26-1.
AT91SAM7X512/256/128 Preliminary 26.3 26.3.1 Product Dependencies I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. 26.3.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller.
Figure 26-3. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 26.4.2 26.4.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
AT91SAM7X512/256/128 Preliminary Figure 26-4. Start Bit Detection Sampling Clock DRXD True Start Detection D0 Baud Rate Clock Figure 26-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD D0 D1 True Start Detection Sampling 26.4.2.3 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set.
26.4.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1.
AT91SAM7X512/256/128 Preliminary 26.4.3.2 Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure.
26.4.4 Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. The RXRDY bit triggers the PDC channel data transfer of the receiver.
AT91SAM7X512/256/128 Preliminary Figure 26-12. Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter 26.4.6 TXD VDD Disabled Disabled RXD TXD Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
26.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
AT91SAM7X512/256/128 Preliminary 26.5 Debug Unit User Interface Table 26-2.
26.5.1 Debug Unit Control Register Name: DBGU_CR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. • RSTTX: Reset Transmitter 0 = No effect.
AT91SAM7X512/256/128 Preliminary 26.5.
26.5.
AT91SAM7X512/256/128 Preliminary 26.5.
26.5.
AT91SAM7X512/256/128 Preliminary 26.5.6 Debug Unit Status Register Name: DBGU_SR Access Type: Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
• COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. • COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active.
AT91SAM7X512/256/128 Preliminary 26.5.7 Debug Unit Receiver Holding Register Name: DBGU_RHR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last received character if RXRDY is set. 26.5.
26.5.
AT91SAM7X512/256/128 Preliminary 26.5.
• NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 Size 0 0 0 0 None 0 0 0 1 8K bytes 0 0 1 0 16K bytes 0 0 1 1 32K bytes 0 1 0 0 Reserved 0 1 0 1 64K bytes 0 1 1 0 Reserved 0 1 1 1 128K bytes 1 0 0 0 Reserved 1 0 0 1 256K bytes 1 0 1 0 512K bytes 1 0 1 1 Reserved 1 1 0 0 1024K bytes 1 1 0 1 Reserved 1 1 1 0 2048K bytes 1 1 1 1 Reserved • SRAMSIZ: Internal SRAM Size SRAMSIZ 224 Size 0 0 0 0 Reserved 0 0 0 1 1
AT91SAM7X512/256/128 Preliminary • ARCH: Architecture Identifier ARCH Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x39 0011 1001 CAP9 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0101 0000 AT91SAM7Axx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x71 0111 0001 AT91SAM7XCxx Series 0x72 0111 0010 AT91SAM7SExx Series
26.5.11 Debug Unit Chip ID Extension Register Name: DBGU_EXID Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. 26.5.
AT91SAM7X512/256/128 Preliminary 27. Parallel Input/Output Controller (PIO) 27.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
27.2 Block Diagram Figure 27-1. Block Diagram PIO Controller AIC PMC PIO Interrupt PIO Clock Data, Enable Up to 32 peripheral IOs Embedded Peripheral PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB 27.3 Application Block Diagram Figure 27-2.
AT91SAM7X512/256/128 Preliminary 27.4 27.4.1 Product Dependencies Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e.
27.5 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 27-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 27-3.
AT91SAM7X512/256/128 Preliminary 27.5.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pullup Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller.
AT91SAM7X512/256/128 Preliminary Figure 27-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 APB Access Write PIO_CODR Write PIO_ODSR at 0 APB Access PIO_ODSR 2 cycles 2 cycles PIO_PDSR 27.5.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.
Figure 27-5. Input Glitch Filter Timing MCK up to 1.5 cycles Pin Level 1 cycle 1 cycle 1 cycle 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 27.5.10 up to 2.5 cycles 1 cycle up to 2 cycles Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line.
AT91SAM7X512/256/128 Preliminary 27.6 I/O Lines Programming Example The programing example as shown in Table 27-1 below is used to define the following configuration.
27.7 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 27-2.
AT91SAM7X512/256/128 Preliminary Table 27-2.
27.7.1 PIO Controller PIO Enable Register Name: PIO_PER Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 27.7.
AT91SAM7X512/256/128 Preliminary 27.7.3 PIO Controller PIO Status Register Name: PIO_PSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active).
27.7.5 PIO Controller Output Disable Register Name: PIO_ODR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line. 27.7.
AT91SAM7X512/256/128 Preliminary 27.7.7 PIO Controller Input Filter Enable Register Name: PIO_IFER Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. 27.7.
27.7.9 PIO Controller Input Filter Status Register Name: PIO_IFSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. 27.7.
AT91SAM7X512/256/128 Preliminary 27.7.11 PIO Controller Clear Output Data Register Name: PIO_CODR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 27.7.
27.7.13 PIO Controller Pin Data Status Register Name: PIO_PDSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. 27.7.
AT91SAM7X512/256/128 Preliminary 27.7.15 PIO Controller Interrupt Disable Register Name: PIO_IDR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. 27.
27.7.17 PIO Controller Interrupt Status Register Name: PIO_ISR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
AT91SAM7X512/256/128 Preliminary 27.7.19 PIO Multi-driver Disable Register Name: PIO_MDDR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line. 27.7.
27.7.21 PIO Pull Up Disable Register Name: PIO_PUDR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line. 27.7.
AT91SAM7X512/256/128 Preliminary 27.7.23 PIO Pull Up Status Register Name: PIO_PUSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. 27.7.
27.7.25 PIO Peripheral B Select Register Name: PIO_BSR Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function. 27.7.
AT91SAM7X512/256/128 Preliminary 27.7.27 PIO Output Write Enable Register Name: PIO_OWER Access Type: Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. 27.7.
27.7.29 PIO Output Write Status Register Name: PIO_OWSR Access Type: Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line.
AT91SAM7X512/256/128 Preliminary 28. Serial Peripheral Interface (SPI) 28.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
28.2 Block Diagram Figure 28-1. Block Diagram PDC APB SPCK MISO PMC MOSI MCK SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 28.3 Application Block Diagram Figure 28-2.
AT91SAM7X512/256/128 Preliminary 28.4 Signal Description Table 28-1. Signal Description Type Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input 28.5 28.5.
28.6 28.6.1 Functional Description Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode.
AT91SAM7X512/256/128 Preliminary Figure 28-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 6 5 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB MISO (from slave) MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 28-4.
28.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register.
AT91SAM7X512/256/128 Preliminary 28.6.3.1 Master Mode Block Diagram Figure 28-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TD SPI_CSR0..
28.6.3.2 Master Mode Flow Diagram Figure 28-6. Master Mode Flow Diagram S SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
AT91SAM7X512/256/128 Preliminary 28.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
• Fixed Peripheral Select: SPI exchanges data with only one peripheral • Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral.
AT91SAM7X512/256/128 Preliminary To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. Figure 28-8 shows different peripheral deselection cases and the effect of the CSAAT bit. Figure 28-8. Peripheral Deselection CSAAT = 0 TDRE NPCS[0..
28.6.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0.
AT91SAM7X512/256/128 Preliminary 28.7 Serial Peripheral Interface (SPI) User Interface Table 28-3.
28.7.1 SPI Control Register Name: SPI_CR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer.
AT91SAM7X512/256/128 Preliminary 28.7.2 SPI Mode Register Name: SPI_MR Access Type: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 3 7 6 5 4 LLB – – MODFDIS PCS 2 1 0 PCSDEC PS MSTR • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select.
PCS = 1111 forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default.
AT91SAM7X512/256/128 Preliminary 28.7.3 SPI Receive Data Register Name: SPI_RDR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
28.7.4 SPI Transmit Data Register Name: SPI_TDR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
AT91SAM7X512/256/128 Preliminary 28.7.
0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. • SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. Note: 1. 272 SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC.
AT91SAM7X512/256/128 Preliminary 28.7.
28.7.
AT91SAM7X512/256/128 Preliminary 28.7.
28.7.9 SPI Chip Select Register Name: SPI_CSR0... SPI_CSR3 Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 4 BITS 3 2 1 0 CSAAT – NCPHA CPOL • CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK).
AT91SAM7X512/256/128 Preliminary • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCK SPCK Baudrate = --------------SCBR Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
AT91SAM7X512/256/128 Preliminary 6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary 29. Two-wire Interface (TWI) 29.1 Overview The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel two-wire bus Serial EEPROM. The TWI is programmable as a master with sequential or single-byte access.
29.4 29.4.1 Product Dependencies I/O Lines Description Table 29-1. 29.4.2 I/O Lines Description Pin Name Pin Description Type TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output I/O Lines Both TWD and TWCK are bi-directional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 29-2 on page 279). When the bus is free, both lines are high.
AT91SAM7X512/256/128 Preliminary 29.5 29.5.1 Functional Description Transfer format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 29-4 on page 281). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 29-3 on page 281). • A high-to-low transition on the TWD line while TWCK is high defines the START condition.
sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in the control register starts the transmission. The data is shifted in the internal shifter and when an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see Figure 296 below).
AT91SAM7X512/256/128 Preliminary Figure 29-8. Master Read with One Byte Internal Address and Multiple Data Bytes TWD S DADR W A IADR(7:0) A S DADR R A DATA A DATA N P TXCOMP Write START Bit Write STOP Bit RXRDY Read RHR Read RHR • S = Start • P = Stop • W = Write • R = Read • A = Acknowledge • N = Not Acknowledge • DADR= Device Address • IADR = Internal Address Figure 29-9 below shows a byte write to an Atmel AT24LC512 EEPROM.
29.5.4 Read/Write Flowcharts The following flowcharts shown in Figure 29-10 and in Figure 29-11 on page 285 give examples for read and write operations in Master Mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 29-10.
AT91SAM7X512/256/128 Preliminary Figure 29-11.
29.6 TWI User Interface 29.6.1 Register Mapping Table 29-2.
AT91SAM7X512/256/128 Preliminary 29.6.2 TWI Control Register Register Name: TWI_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 – 4 – 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
29.6.3 TWI Master Mode Register Register Name: TWI_MMR Address Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 DADR 18 17 16 15 – 14 – 13 – 12 MREAD 11 – 10 – 9 7 – 6 – 5 – 4 – 3 – 2 – 1 – 8 IADRSZ 0 – • IADRSZ: Internal Device Address Size Table 29-3.
AT91SAM7X512/256/128 Preliminary 29.6.4 TWI Internal Address Register Register Name: TWI_IADR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. – Low significant byte address in 10-bit mode addresses.
29.6.
AT91SAM7X512/256/128 Preliminary 29.6.6 TWI Status Register Register Name: TWI_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 – 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed 0 = In master, during the length of the current frame. In slave, from START received to STOP received.
29.6.7 TWI Interrupt Enable Register Register Name: TWI_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 – 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • NACK: Not Acknowledge 0 = No effect. 1 = Enables the corresponding interrupt.
AT91SAM7X512/256/128 Preliminary 29.6.8 TWI Interrupt Disable Register Register Name: TWI_IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 – 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • NACK: Not Acknowledge 0 = No effect.
29.6.9 TWI Interrupt Mask Register Register Name: TWI_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NACK 7 – 6 – 5 – 4 – 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • NACK: Not Acknowledge 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
AT91SAM7X512/256/128 Preliminary 29.6.
29.6.
AT91SAM7X512/256/128 Preliminary 30. Universal Synchronous Asynchronous Receiver Transceiver (USART) 30.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
30.2 Block Diagram Figure 30-1.
AT91SAM7X512/256/128 Preliminary 30.3 Application Block Diagram Figure 30-2. Application Block Diagram IrLAP PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrDA Driver USART RS232 Drivers RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers Modem PSTN 30.4 I/O Lines Description Table 30-1.
30.5 30.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
AT91SAM7X512/256/128 Preliminary 30.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 30-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD SCK 0 1 16-bit Counter 2 FIDI >1 3 1 0 SYNC OVER 0 0 Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 30.6.1.
AT91SAM7X512/256/128 Preliminary Table 30-2. Baud Rate Example (OVER = 0) (Continued) Source Clock Expected Baud Rate Calculation Result CD Actual Baud Rate Error 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.
Figure 30-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 16-bit Counter 2 3 glitch-free logic 1 0 FIDI >1 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC USCLKS = 3 30.6.1.4 Sampling Clock Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR.
AT91SAM7X512/256/128 Preliminary Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 30-3. Table 30-3. Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 30-4. Table 30-4.
Figure 30-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 30.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR).
AT91SAM7X512/256/128 Preliminary Figure 30-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 30-8 and Figure 30-9 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 30-8.
AT91SAM7X512/256/128 Preliminary Figure 30-10. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 30.6.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set.
30.6.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page 311. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd.
AT91SAM7X512/256/128 Preliminary Figure 30-12. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 30.6.3.6 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
Figure 30-13. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 30-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 30-7. 30.6.3.8 Maximum Timeguard Length Depending on Baud Rate Baud Rate Bit time Timeguard Bit/sec µs ms 1 200 833 212.
AT91SAM7X512/256/128 Preliminary • Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received.
Table 30-8. 30.6.3.9 Maximum Time-out Period (Continued) Baud Rate Bit Time Time-out 56000 18 1 170 57600 17 1 138 200000 5 328 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR).
AT91SAM7X512/256/128 Preliminary The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored.
Figure 30-17. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2.
AT91SAM7X512/256/128 Preliminary 30.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 30.6.4.
If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 30-21. If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 30-22. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time.
AT91SAM7X512/256/128 Preliminary If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1.
30.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 30-9. Table 30-9. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 Kb/s 78.13 µs 9.6 Kb/s 19.53 µs 19.2 Kb/s 9.77 µs 38.4 Kb/s 4.88 µs 57.6 Kb/s 3.26 µs 115.2 Kb/s 1.63 µs Figure 30-24 shows an example of character transmission. Figure 30-24.
AT91SAM7X512/256/128 Preliminary Table 30-10. IrDA Baud Rate Error (Continued) Peripheral Clock 30.6.5.3 Baud Rate CD Baud Rate Error Pulse Time 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.
30.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 30-26. Figure 30-26.
AT91SAM7X512/256/128 Preliminary 30.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI.
Figure 30-28. Normal Mode Configuration RXD Receiver TXD Transmitter 30.6.8.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 30-29. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 30-29. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 30.6.8.
AT91SAM7X512/256/128 Preliminary Figure 30-31.
30.7 USART User Interface Table 30-12.
AT91SAM7X512/256/128 Preliminary 30.7.1 USART Control Register Name: US_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter.
• STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set.
AT91SAM7X512/256/128 Preliminary 30.7.
• SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • PAR: Parity Type PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode • NBSTOP: Number of Stop Bits NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.
AT91SAM7X512/256/128 Preliminary • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line.
30.7.
AT91SAM7X512/256/128 Preliminary 30.7.
30.7.
AT91SAM7X512/256/128 Preliminary 30.7.6 USART Channel Status Register Name: US_CSR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITERATION 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled.
• TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). • TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There is at least one character in either US_THR or the Transmit Shift Register.
AT91SAM7X512/256/128 Preliminary • CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1.
30.7.7 USART Receive Holding Register Name: US_RHR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. 30.7.
AT91SAM7X512/256/128 Preliminary 30.7.
30.7.10 USART Receiver Time-out Register Name: US_RTOR Access Type: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 30.7.
AT91SAM7X512/256/128 Preliminary 30.7.12 USART FI DI RATIO Register Name: US_FIDI Access Type: Read/Write Reset Value : 0x174 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal.
30.7.14 USART IrDA FILTER Register Name: US_IF Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
AT91SAM7X512/256/128 Preliminary 31. Synchronous Serial Controller (SSC) 31.1 Overview The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
31.2 Block Diagram Figure 31-1. Block Diagram ASB APB Bridge PDC APB TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 31.3 Application Block Diagram Figure 31-2.
AT91SAM7X512/256/128 Preliminary 31.4 Pin Name List Table 31-1. I/O Lines Description Pin Name Pin Description RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output 31.5 31.5.1 Type Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
Figure 31-3.
AT91SAM7X512/256/128 Preliminary 31.6.1.1 Clock Divider Figure 31-4. Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter.
TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 31-6. Transmitter Clock Management SSC_TCMR.CKS SSC_TCMR.CKO TK Receiver Clock TK Divider Clock 0 Transmitter Clock 1 SSC_TCMR.CKI 31.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad.
AT91SAM7X512/256/128 Preliminary 31.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 350. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 352.
When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. Figure 31-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF Start Selector SSC_RFMR.MSBF SSC_RFMR.
AT91SAM7X512/256/128 Preliminary Figure 31-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) TD (Output) B1 BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 31-11.
31.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported.
AT91SAM7X512/256/128 Preliminary 31.6.6.1 31.6.7 Compare Functions Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last FSLEN bits received at the FSLEN lower bit of the data contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs.
Table 31-3.
AT91SAM7X512/256/128 Preliminary Figure 31-14. Transmit Frame Format in Continuous Mode Start Data TD Default Data From SSC_THR From SSC_THR DATLEN DATLEN Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 31-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Note: 31.6.
Figure 31-16. Interrupt Block Diagram SSC_IMR SSC_IER PDC SSC_IDR Set Clear TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC Interrupt Control RXBUFF ENDRX SSC Interrupt Receiver RXRDY OVRUN RXSYNC 31.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 31-17.
AT91SAM7X512/256/128 Preliminary Figure 31-18. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC CODEC TD Serial Data In RD RF Serial Data Clock (SCLK) RK Frame sync (FSYNC) First Time Slot Dstart Dend Serial Data Out Serial Data In Figure 31-19.
AT91SAM7X512/256/128 Preliminary 31.8 Synchronous Serial Controller (SSC) User Interface Table 31-4.
AT91SAM7X512/256/128 Preliminary 31.8.1 SSC Control Register Name: SSC_CR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0: No effect. 1: Disables Receive.
AT91SAM7X512/256/128 Preliminary 31.8.2 SSC Clock Mode Register Name: SSC_CMR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV • DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
AT91SAM7X512/256/128 Preliminary 31.8.
AT91SAM7X512/256/128 Preliminary • CKG: Receive Clock Gating Selection CKG Receive Clock Gating 0x0 None, continuous clock 0x1 Receive Clock enabled only if RF Low 0x2 Receive Clock enabled only if RF High 0x3 Reserved • START: Receive Start Selection START Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
AT91SAM7X512/256/128 Preliminary 31.8.4 SSC Receive Frame Mode Register Name: SSC_RFMR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
AT91SAM7X512/256/128 Preliminary • FSOS: Receive Frame Sync Output Selection FSOS Selected Receive Frame Sync Signal RF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Input-only Reserved Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Reg
AT91SAM7X512/256/128 Preliminary 31.8.
AT91SAM7X512/256/128 Preliminary • START: Transmit Start Selection START Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
AT91SAM7X512/256/128 Preliminary 31.8.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 FSDEN 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
AT91SAM7X512/256/128 Preliminary • FSOS: Transmit Frame Sync Output Selection FSOS Selected Transmit Frame Sync Signal TF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6-0x7 Reserved Input-only Undefined • FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal.
AT91SAM7X512/256/128 Preliminary 31.8.7 SSC Receive Holding Register Name: SSC_RHR Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 31.8.
AT91SAM7X512/256/128 Preliminary 31.8.9 SSC Receive Synchronization Holding Register Name: SSC_RSHR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT • RSDAT: Receive Synchronization Data 31.8.
AT91SAM7X512/256/128 Preliminary 31.8.
AT91SAM7X512/256/128 Preliminary 31.8.
AT91SAM7X512/256/128 Preliminary 31.8.13 SSC Status Register Name: SSC_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty.
AT91SAM7X512/256/128 Preliminary • TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. • RXSYN: Receive Sync 0: An Rx Sync has not occurred since the last read of the Status Register. 1: An Rx Sync has occurred since the last read of the Status Register. • TXEN: Transmit Enable 0: Transmit is disabled. 1: Transmit is enabled. • RXEN: Receive Enable 0: Receive is disabled. 1: Receive is enabled.
AT91SAM7X512/256/128 Preliminary 31.8.14 SSC Interrupt Enable Register Name: SSC_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0: No effect.
AT91SAM7X512/256/128 Preliminary • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt.
AT91SAM7X512/256/128 Preliminary 31.8.15 SSC Interrupt Disable Register Name: SSC_IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0: No effect.
AT91SAM7X512/256/128 Preliminary • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt.
AT91SAM7X512/256/128 Preliminary 31.8.16 SSC Interrupt Mask Register Name: SSC_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled.
AT91SAM7X512/256/128 Preliminary • TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled. • RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled.
AT91SAM7X512/256/128 Preliminary 32. Timer/Counter (TC) 32.1 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.
32.2 Block Diagram Figure 32-1.
AT91SAM7X512/256/128 Preliminary 32.3 Pin Name List Table 32-3. 32.4 32.4.1 TC pin list Pin Name Description Type TCLK0-TCLK2 External Clock Input Input TIOA0-TIOA2 I/O Line A I/O TIOB0-TIOB2 I/O Line B I/O Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 32.4.
32.5 Functional Description 32.5.1 TC Description The three channels of the Timer/Counter are independent and identical in operation. The registers for channel programming are listed in Table 32-5 on page 397. 32.5.1.1 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock.
AT91SAM7X512/256/128 Preliminary Figure 32-2. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 CLKI TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Selected Clock XC0 XC1 XC2 BURST 1 32.5.1.3 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 32-3. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register.
Figure 32-3. Clock Control Selected Clock Trigger CLKSTA CLKEN Q Q S CLKDIS S R R Counter Clock 32.5.1.4 Stop Event Disable Event TC Operating Modes Each channel can independently operate in two different modes: • Capture Mode provides measurement on signals. • Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs.
AT91SAM7X512/256/128 Preliminary If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 32.5.
MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST CLKI R S OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS INT Figure 32-4.
AT91SAM7X512/256/128 Preliminary 32.5.3 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TCCLKS TIOB MTIOB TIOA MTIOA
AT91SAM7X512/256/128 Preliminary 32.5.3.2 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 32-6. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 32-7. RC Compare cannot be programmed to generate a trigger in this configuration.
Figure 32-7. WAVSEL= 00 with trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA 32.5.3.3 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 32-8.
AT91SAM7X512/256/128 Preliminary Figure 32-8. WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 32-9. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA 32.5.3.4 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF.
RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 32-10. WAVSEL = 01 Without Trigger Counter decremented by compare match with 0xFFFF Counter Value 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 32-11.
AT91SAM7X512/256/128 Preliminary A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 32-13. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 32-12.
The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA.
AT91SAM7X512/256/128 Preliminary 32.6 Timer/Counter (TC) User Interface 32.6.1 Global Register Mapping Table 32-4.
32.6.3 TC Block Control Register Register Name: TC_BCR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
AT91SAM7X512/256/128 Preliminary 32.6.
32.6.5 TC Channel Control Register Register Name: TC_CCR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock.
AT91SAM7X512/256/128 Preliminary 32.6.
• ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. • WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled).
AT91SAM7X512/256/128 Preliminary 32.6.
• EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • EEVT: External Event Selection EEVT Signal selected as external event TIOB Direction 0 0 TIOB input(1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
AT91SAM7X512/256/128 Preliminary • ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPC: RC Compare Effect on TIOB BCPC Effect 0 0 none 0 1 set
• BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG 406 Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle AT91SAM7X512/256/128 Preliminary 6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary 32.6.8 TC Counter Value Register Register Name: TC_CV Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time.
32.6.9 TC Register A Register Name: TC_RA Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real time.
AT91SAM7X512/256/128 Preliminary 32.6.10 TC Register B Register Name: TC_RB Access Type: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time. 32.6.
32.6.12 TC Status Register Register Name: TC_SR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register.
AT91SAM7X512/256/128 Preliminary • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high.
32.6.13 TC Interrupt Enable Register Register Name: TC_IER Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt.
AT91SAM7X512/256/128 Preliminary 32.6.14 TC Interrupt Disable Register Register Name: TC_IDR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect.
32.6.15 TC Interrupt Mask Register Register Name: TC_IMR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled.
AT91SAM7X512/256/128 Preliminary 33. Pulse Width Modulation Controller (PWM) 33.1 Overview The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock.
33.3 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 33-1. 33.4 33.4.1 I/O Line Description Name Description Type PWMx PWM Waveform Output for channel x Output Product Dependencies I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function.
AT91SAM7X512/256/128 Preliminary 33.5 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. • Clocked by the system clock, MCK, the clock generator module provides 13 clocks. • Each channel can independently choose one of the clock generator outputs. • Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 33.5.1 PWM Clock Generator Figure 33-2.
Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR). After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off.
AT91SAM7X512/256/128 Preliminary By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: (----------------------------------------CRPD × DIVA )( CRPD × DIVAB ) or ---------------------------------------------MCK MCK If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512,
When center aligned, the internal channel counter increases up to CPRD and decreases down to 0. This ends the period. When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel.
AT91SAM7X512/256/128 Preliminary Figure 33-5.
33.5.3 33.5.3.1 PWM Controller Operations Initialization Before enabling the output channel, this channel must have been configured by the software application: • Configuration of the clock generator if DIVA and DIVB are required • Selection of the clock for each channel (CPRE field in the PWM_CMRx register) • Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) • Configuration of the period for each channel (CPRD in the PWM_CPRDx register).
AT91SAM7X512/256/128 Preliminary Figure 33-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 0 1 PWM_CPRDx PWM_CMRx. CPD PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level.
33.5.3.4 Interrupts Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.
AT91SAM7X512/256/128 Preliminary 33.6 Pulse Width Modulation Controller (PWM) User Interface Table 33-2.
33.6.1 PWM Mode Register Register Name: PWM_MR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 26 23 22 21 20 19 18 11 10 25 24 17 16 9 8 1 0 PREB DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB CLKA, CLKB 0 CLKA, CLKB clock is turned off 1 CLKA, CLKB clock is clock selected by PREA, PREB 2-255 CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor. • PREA, PREB PREA, PREB 0 0 0 0 MCK.
AT91SAM7X512/256/128 Preliminary 33.6.2 PWM Enable Register Register Name: PWM_ENA Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. 33.6.
33.6.4 PWM Status Register Register Name: PWM_SR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled. 33.6.
AT91SAM7X512/256/128 Preliminary 33.6.6 PWM Interrupt Disable Register Register Name: PWM_IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x.
33.6.7 PWM Interrupt Mask Register Register Name: PWM_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled. 33.6.
AT91SAM7X512/256/128 Preliminary 33.6.
33.6.10 PWM Channel Duty Cycle Register Register Name: PWM_CDTYx Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (internal channel counter size) are significative. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx). 33.6.
AT91SAM7X512/256/128 Preliminary (----------------------------------------CRPD × DIVA )( CRPD × DIVAB ) or ---------------------------------------------MCK MCK If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: – By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024).
33.6.12 PWM Channel Counter Register Register Name: PWM_CCNTx Access Type: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT • CNT: Channel Counter Register Internal counter value. This register is reset when: – the channel is enabled (writing CHIDx in the PWM_ENA register). – the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned. 33.6.
AT91SAM7X512/256/128 Preliminary 34. USB Device Port (UDP) 34.1 Overview The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
34.2 Block Diagram Figure 34-1. Block Diagram Atmel Bridge MCK APB to MCU Bus UDPCK USB Device txoen U s e r I n t e r f a c e udp_int external_resume W r a p p e r Dual Port RAM FIFO W r a p p e r eopn Serial Interface Engine 12 MHz SIE txd rxdm Embedded USB Transceiver DP DM rxd rxdp Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain Access to the UDP is via the APB bus interface.
AT91SAM7X512/256/128 Preliminary 34.3 Product Dependencies For further details on the USB Device hardware implementation, see the specific Product Properties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are available from the product boundary. Two I/O lines may be used by the application: • One to check that VBUS is still available from the host.
34.4 Typical Connection Figure 34-2. Board Schematic to Interface USB Device Peripheral 5V Bus Monitoring PIO 27 K 47 K 3V3 Pullup Control PIO 0: Enable 1: Disable 1.5K REXT DDM 2 1 3 Type B 4 Connector DDP REXT 330 K 34.4.1 330 K USB Device Transceiver The USB device transceiver is embedded in the product.
AT91SAM7X512/256/128 Preliminary A termination serial resistor must be connected to DP and DM. The resistor value is defined in the electrical specification of the product (REXT).
34.5 Functional Description 34.5.1 USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows. Figure 34-3. Example of USB V2.0 Full-speed Communication Control USB Host V2.
AT91SAM7X512/256/128 Preliminary 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction 34.5.1.3 USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 34-3.
Figure 34-4. Control Read and Write Sequences Setup Stage Control Read Setup TX Data Stage Data OUT TX Setup Stage Control Write No Data Control Notes: Setup TX Status Stage Data OUT TX Data Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Data IN TX Status IN TX Status Stage Status OUT TX 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID.
AT91SAM7X512/256/128 Preliminary Figure 34-5. Setup Transaction Followed by a Data OUT Transaction Setup Received USB Bus Packets Setup PID Data Setup RXSETUP Flag Setup Handled by Firmware ACK PID Data OUT PID Data OUT Data OUT PID Data OUT ACK PID Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) 34.5.2.
Figure 34-6. Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX USB Bus Packets Data IN PID Microcontroller Load Data in FIFO Data IN 1 ACK PID Data IN PID NAK PID Data is Sent on USB Bus Data IN PID ACK PID Data IN 2 TXPKTRDY Flag (UDP_CSRx) Set by the firmware Cleared by Hw Set by the firmware Cleared by Hw Interrupt Pending Interrupt Pending TXCOMP Flag (UDP_CSRx) Payload in FIFO Cleared by Firmware DPR access by the firmware FIFO (DPR) Content 34.5.2.
AT91SAM7X512/256/128 Preliminary When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_ CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_ FDRx register. 3.
34.5.2.5 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. 34.5.2.6 Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint.
AT91SAM7X512/256/128 Preliminary 34.5.2.7 Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 34-10.
10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s UDP_ FDRx register. 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s UDP_ CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. Figure 34-11.
AT91SAM7X512/256/128 Preliminary 1. The microcontroller sets the FORCESTALL flag in the UDP_ CSRx endpoint’s register. 2. The host receives the stall packet. 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt.
34.5.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 34-14.
AT91SAM7X512/256/128 Preliminary 34.5.3.1 Not Powered State Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM lines are pulled down by 330 KΩ resistors. 34.5.3.
34.5.3.6 Entering in Suspend State When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500uA from the 5V VBUS.
AT91SAM7X512/256/128 Preliminary Figure 34-15. Board Schematic to Drive a K State 3V3 PIO 0: Force Wake UP (K State) 1: Normal Mode 1.
34.6 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register. Table 34-4.
AT91SAM7X512/256/128 Preliminary 34.6.1 UDP Frame Number Register Register Name: UDP_ FRM_NUM Access Type: Read-only 31 --- 30 --- 29 --- 28 --- 27 --- 26 --- 25 --- 24 --- 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame.
34.6.2 UDP Global State Register Register Name: UDP_ GLB_STAT Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 – 3 – 2 – 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state.
AT91SAM7X512/256/128 Preliminary 34.6.
34.6.
AT91SAM7X512/256/128 Preliminary 34.6.
34.6.6 UDP Interrupt Mask Register Register Name: UDP_ IMR Access Type: Read-only Note: 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12(1) – 11 SOFINT 10 – 9 8 RXRSM RXSUSP 7 6 5 EP5INT 4 EP4INT 3 EP3INT 2 EP2INT 1 EP1INT 0 EP0INT 1. Bit 12 of UDP_IMR cannot be masked and is always read at 1.
AT91SAM7X512/256/128 Preliminary 34.6.
This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration.
AT91SAM7X512/256/128 Preliminary 34.6.8 UDP Interrupt Clear Register Register Name: UDP_ ICR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 – 9 RXRSM 8 RXSUSP 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt.
34.6.
AT91SAM7X512/256/128 Preliminary 34.6.10 UDP Endpoint Control and Status Register Register Name: UDP_ CSRx [x = 0..
When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. • RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available.
AT91SAM7X512/256/128 Preliminary Write: 0 = No effect. 1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_ FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one.
• EPTYPE[2:0]: Endpoint Type Read/Write 000 Control 001 Isochronous OUT 101 Isochronous IN 010 Bulk OUT 110 Bulk IN 011 Interrupt OUT 111 Interrupt IN • DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. • EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint.
AT91SAM7X512/256/128 Preliminary 34.6.11 UDP FIFO Data Register Register Name: UDP_ FDRx [x = 0..5] Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register.
34.6.12 UDP Transceiver Control Register Register Name: UDP_ TXVC Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register.
AT91SAM7X512/256/128 Preliminary 35. Analog-to-Digital Converter (ADC) 35.1 Overview The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates an 8-to-1 analog multiplexer, making possible the analog-todigital conversions of 8 analog lines. The conversions extend from 0V to ADVREF.
35.3 Signal Description Table 35-1.
AT91SAM7X512/256/128 Preliminary 35.4 35.4.1 Product Dependencies Power Management The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into Sleep Mode, the Power Management Controller has no effect on the ADC behavior. 35.4.2 Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller.
35.5 35.5.1 Functional Description Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the ”ADC Mode Register” on page 481 and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F).
AT91SAM7X512/256/128 Preliminary 35.5.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt.
If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (ADC_SR). In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in ADC_SR. The OVRE and GOVRE flags are automatically cleared when ADC_SR is read. Figure 35-3.
AT91SAM7X512/256/128 Preliminary 35.5.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR).
35.5.7 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register ADC_MR. In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC.
AT91SAM7X512/256/128 Preliminary 35.6 Analog-to-digital Converter (ADC) User Interface Table 35-2.
35.6.1 ADC Control Register Register Name: ADC_CR Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – START SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion.
AT91SAM7X512/256/128 Preliminary 35.6.2 ADC Mode Register Register Name: ADC_MR Access Type: Read/Write 31 30 29 28 – – – – 23 22 21 20 – – – 15 14 13 – – 27 26 25 24 17 16 10 9 8 2 1 SHTIM 19 18 STARTUP 12 11 PRESCAL 7 6 5 4 – – SLEEP LOWRES 3 TRGSEL 0 TRGEN • TRGEN: Trigger Enable TRGEN Selected TRGEN 0 Hardware triggers are disabled. Starting a conversion is only possible by software. 1 Hardware trigger selected by TRGSEL field is enabled.
• PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 ) • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock • SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+1) / ADCClock 482 AT91SAM7X512/256/128 Preliminary 6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary 35.6.3 ADC Channel Enable Register Register Name: ADC_CHER Access Type: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel. 35.6.
35.6.5 ADC Channel Status Register Register Name: ADC_CHSR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled.
AT91SAM7X512/256/128 Preliminary 35.6.6 ADC Status Register Register Name: ADC_SR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – RXBUFF ENDRX GOVRE DRDY 15 14 13 12 11 10 9 8 OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0 7 6 5 4 3 2 1 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished.
35.6.7 ADC Last Converted Data Register Register Name: ADC_LCDR Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – – – 7 6 5 4 3 2 8 LDATA 1 0 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
AT91SAM7X512/256/128 Preliminary 35.6.
35.6.
AT91SAM7X512/256/128 Preliminary 35.6.
35.6.11 ADC Channel Data Register Register Name: ADC_CDRx Access Type: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – – – 7 6 5 4 3 2 8 DATA 1 0 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
AT91SAM7X512/256/128 Preliminary 36. Controller Area Network (CAN) 36.1 Description The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/sec.
36.2 Block Diagram Figure 36-1.
AT91SAM7X512/256/128 Preliminary 36.3 Application Block Diagram Figure 36-2. 36.4 Application Block Diagram Layers Implementation CAN-based Profiles Software CAN-based Application Layer Software CAN Data Link Layer CAN Controller CAN Physical Layer Transceiver I/O Lines Description Table 36-1. I/O Lines Description Name Description Type CANRX CAN Receive Serial Data Input CANTX CAN Transmit Serial Data Output 36.5 36.5.
AT91SAM7X512/256/128 Preliminary 36.6 CAN Controller Features 36.6.1 CAN Protocol Overview The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports real-time control with a very high level of security with bit rates up to 1 Mbit/s. The CAN protocol supports four different frame types: • Data frames: They carry data from a transmitter node to the receiver nodes.
AT91SAM7X512/256/128 Preliminary Figure 36-3. Message Acceptance Procedure CAN_MAMx CAN_MIDx Message Received & & == No Message Refused Yes Message Accepted CAN_MFIDx If a mailbox is dedicated to receiving several messages (a family of messages) with different IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the CAN_MIDx.
AT91SAM7X512/256/128 Preliminary 36.6.2.2 Receive Mailbox When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID. If such a mailbox is found, then the message is stored in its data registers.
AT91SAM7X512/256/128 Preliminary 36.6.3 Time Management Unit The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR register).
AT91SAM7X512/256/128 Preliminary 36.6.4 36.6.4.1 CAN 2.0 Standard Features CAN Bit Timing Configuration All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments. The CAN protocol specification partitions the nominal bit time into four different segments: Figure 36-4.
AT91SAM7X512/256/128 Preliminary The SAMPLE POINT is the point in time at which the bus level is read and interpreted as the value of that respective bit. Its location is at the end of PHASE_SEG1. SJW: ReSynchronization Jump Width. The ReSynchronization Jump Width defines the limit to the amount of lengthening or shortening of the Phase Segments. SJW is programmable to be the minimum of PHASE SEG1 and 4 TQ.
AT91SAM7X512/256/128 Preliminary CAN baudrate= 500kbit/s => bit time= 2us Delay of the bus driver: 50 ns Delay of the receiver: 30ns Delay of the bus line (20m): 110ns The total number of time quanta in a bit time must be comprised between 8 and 25.
AT91SAM7X512/256/128 Preliminary CAN Bus Synchronization Two types of synchronization are distinguished: “hard synchronization” at the start of a frame and “resynchronization” inside a frame. After a hard synchronization, the bit time is restarted with the end of the SYNC_SEG segment, regardless of the phase error. Resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge.
AT91SAM7X512/256/128 Preliminary 36.6.4.2 Error Detection There are five different error types that are not mutually exclusive. Each error concerns only specific fields of the CAN data frame (refer to the Bosch CAN specification for their correspondence): • CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data Field.
AT91SAM7X512/256/128 Preliminary An error active unit takes part in bus communication and sends an active error frame when the CAN controller detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further transmission. A bus off unit is not allowed to have any influence on the bus.
AT91SAM7X512/256/128 Preliminary 36.6.5.1 Enabling Low-power Mode A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN controller enters Low-power Mode once all pending transmit messages are sent. When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while SLEEP is set.
AT91SAM7X512/256/128 Preliminary To disable Low-power Mode, the software application must: – Enable the CAN Controller clock. This is done by programming the Power Management Controller (PMC). – Clear the LPM field in the CAN_MR register The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive “recessive” bits. Once synchronized, the WAKEUP signal in the CAN_SR register is set.
AT91SAM7X512/256/128 Preliminary The CAN controller can start listening to the network in Autobaud Mode. In this case, the error counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags, the CAN_BR register values synchronized with the network. Once no error has been detected, the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR register. Figure 36-10.
AT91SAM7X512/256/128 Preliminary • System interrupts – Bus-off interrupt: The CAN module enters the bus-off state. – Error-passive interrupt: The CAN module enters Error Passive Mode. – Error-active Mode: The CAN module is neither in Error Passive Mode nor in Busoff mode. – Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its error counter value exceeds 96. – Wake-up interrupt: This interrupt is generated after a wake-up and a bus synchronization.
AT91SAM7X512/256/128 Preliminary 36.7.3 CAN Controller Message Handling 36.7.3.1 Receive Handling Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is stored in the mailbox data register. In Receive with Overwrite Mode, the last message received is stored in the mailbox. Simple Receive Mailbox A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured.
AT91SAM7X512/256/128 Preliminary A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set.
AT91SAM7X512/256/128 Preliminary If several mailboxes are chained to receive a buffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in Receive Mode. The first message received is handled by the first mailbox, the second one is refused by the first mailbox and accepted by the second mailbox, the last message is accepted by the last mailbox and refused by previous ones (see Figure 36-13). Figure 36-13.
AT91SAM7X512/256/128 Preliminary Figure 36-14. Chaining Three Mailboxes to Receive a Buffer Split into Four Messages Buffer split in 4 messages CAN BUS Message s1 Message s2 Message s3 Message s4 MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz) Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR 36.7.3.
AT91SAM7X512/256/128 Preliminary 0 and mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first. Setting the MACR bit in the CAN_MCRx register aborts the transmission. Transmission for several mailboxes can be aborted by writing MBx fields in the CAN_MACR register. If the message is being sent when the abort command is set, then the application is notified by the MRDY bit set and not the MABT in the CAN_MSRx register.
AT91SAM7X512/256/128 Preliminary Figure 36-16. Producer / Consumer Model Producer Request PUSH MODEL CAN Data Frame Consumer Indication(s) PULL MODEL Producer Indications Response Consumer CAN Remote Frame Request(s) CAN Data Frame Confirmation(s) In Pull Mode, a consumer transmits a remote frame to the producer. When the producer receives a remote frame, it sends the answer accepted by one or many consumers.
AT91SAM7X512/256/128 Preliminary The MRTR field in the CAN_MSRx register has no meaning. This field is used only when using Receive and Receive with Overwrite modes. After a remote frame has been received, the mailbox functions like a transmit mailbox. The message with the highest priority is sent first. The transmitted message may be aborted by setting the MACR bit in the CAN_MCR register. Please refer to the section ”Transmission Handling” on page 511. Figure 36-17.
AT91SAM7X512/256/128 Preliminary Figure 36-18. Consumer Handling Remote Frame CAN BUS Message x Remote Frame Message y MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) (CAN_MDLx CAN_MDHx) 36.7.4 Message y Message x CAN Controller Timing Modes Using the free running 16-bit internal timer, the CAN controller can be set in one of the two following timing modes: • Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame.
AT91SAM7X512/256/128 Preliminary 36.7.4.2 Time Triggered Mode In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window. Figure 36-20.
AT91SAM7X512/256/128 Preliminary is frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated when TOVF is set. Figure 36-21.
AT91SAM7X512/256/128 Preliminary 36.8 Controller Area Network (CAN) User Interface Table 36-4.
AT91SAM7X512/256/128 Preliminary 36.8.1 CAN Mode Register Name: CAN_MR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 25 24 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 DRPT 6 TIMFRZ 5 TTM 4 TEOF 3 OVL 2 ABM 1 LPM 0 CANEN • CANEN: CAN Controller Enable 0 = The CAN Controller is disabled. 1 = The CAN Controller is enabled. • LPM: Disable/Enable Low Power Mode 0 = Disable w Power Mode.
AT91SAM7X512/256/128 Preliminary 36.8.2 CAN Interrupt Enable Register Name: CAN_IER Access Type: Write-only 31 – 30 – 29 – 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Interrupt Enable 0 = No effect. 1 = Enable Mailbox x interrupt. • ERRA: Error Active mode Interrupt Enable 0 = No effect.
AT91SAM7X512/256/128 Preliminary • SERR: Stuffing Error Interrupt Enable 0 = No effect. 1 = Enable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Enable 0 = No effect. 1 = Enable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Enable 0 = No effect. 1 = Enable Form Error interrupt. • BERR: Bit Error Interrupt Enable 0 = No effect. 1 = Enable Bit Error interrupt.
AT91SAM7X512/256/128 Preliminary 36.8.3 CAN Interrupt Disable Register Name: CAN_IDR Access Type: Write-only 31 – 30 – 29 – 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Interrupt Disable 0 = No effect. 1 = Disable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Disable 0 = No effect.
AT91SAM7X512/256/128 Preliminary • SERR: Stuffing Error Interrupt Disable 0 = No effect. 1 = Disable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Disable 0 = No effect. 1 = Disable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Disable 0 = No effect. 1 = Disable Form Error interrupt. • BERR: Bit Error Interrupt Disable 0 = No effect. 1 = Disable Bit Error interrupt.
AT91SAM7X512/256/128 Preliminary 36.8.4 CAN Interrupt Mask Register Name: CAN_IMR Access Type: Read-only 31 – 30 – 29 – 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Interrupt Mask 0 = Mailbox x interrupt is disabled. 1 = Mailbox x interrupt is enabled.
AT91SAM7X512/256/128 Preliminary • SERR: Stuffing Error Interrupt Mask 0 = Bit Stuffing Error interrupt is disabled. 1 = Bit Stuffing Error interrupt is enabled. • AERR: Acknowledgment Error Interrupt Mask 0 = Acknowledgment Error interrupt is disabled. 1 = Acknowledgment Error interrupt is enabled. • FERR: Form Error Interrupt Mask 0 = Form Error interrupt is disabled. 1 = Form Error interrupt is enabled. • BERR: Bit Error Interrupt Mask 0 = Bit Error interrupt is disabled.
AT91SAM7X512/256/128 Preliminary 36.8.5 CAN Status Register Name: CAN_SR Access Type: Read-only 31 OVLSY 30 TBSY 29 RBSY 28 BERR 27 FERR 26 AERR 25 SERR 24 CERR 23 TSTP 22 TOVF 21 WAKEUP 20 SLEEP 19 BOFF 18 ERRP 17 WARN 16 ERRA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 • MBx: Mailbox x Event 0 = No event occurred on Mailbox x. 1 = An event occurred on Mailbox x.
AT91SAM7X512/256/128 Preliminary This flag is automatically reset when Low power mode is disabled • WAKEUP: CAN controller is not in Low power Mode 0 = CAN controller is in low power mode. 1 = CAN controller is not in low power mode. When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the CAN Controller enters Low Power mode.
AT91SAM7X512/256/128 Preliminary A bit error is set when the bit value monitored on the line is different from the bit value sent. This flag is automatically cleared by reading CAN_SR register. • RBSY: Receiver busy 0 = CAN receiver is not receiving a frame. 1 = CAN receiver is receiving a frame. Receiver busy. This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame (remote, data, overload or error frame). It is automatically reset when CAN is not receiving.
AT91SAM7X512/256/128 Preliminary 36.8.6 CAN Baudrate Register Name: CAN_BR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 SMP 23 – 22 21 20 19 BRP 18 17 16 15 – 14 – 13 12 11 – 10 9 PROPAG 8 7 – 6 5 PHASE1 4 3 – 2 1 PHASE2 0 SJW Any modification on one of the fields of the CANBR register must be done while CAN module is disabled. To compute the different Bit Timings, please refer to the Section 36.6.4.1 ”CAN Bit Timing Configuration” on page 498.
AT91SAM7X512/256/128 Preliminary 36.8.7 CAN Timer Register Name: CAN_TIM Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TIMER15 14 TIMER14 13 TIMER13 12 TIMER12 11 TIMER11 10 TIMER10 9 TIMER9 8 TIMER8 7 TIMER7 6 TIMER6 5 TIMER5 4 TIMER4 3 TIMER3 2 TIMER2 1 TIMER1 0 TIMER0 • TIMERx: Timer This field represents the internal CAN controller 16-bit timer value.
AT91SAM7X512/256/128 Preliminary 36.8.
AT91SAM7X512/256/128 Preliminary 36.8.9 CAN Error Counter Register Name: CAN_ECR Access Type: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 TEC 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 REC • REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG.
AT91SAM7X512/256/128 Preliminary 36.8.10 CAN Transfer Command Register Name: CAN_TCR Access Type: Write-only 31 TIMRST 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 This register initializes several transfer requests at the same time. • MBx: Transfer Request for Mailbox x Mailbox Object Type Description Receive It receives the next message.
AT91SAM7X512/256/128 Preliminary 36.8.11 CAN Abort Command Register Name: CAN_ACR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 MB7 6 MB6 5 MB5 4 MB4 3 MB3 2 MB2 1 MB1 0 MB0 This register initializes several abort requests at the same time.
AT91SAM7X512/256/128 Preliminary 36.8.
AT91SAM7X512/256/128 Preliminary 36.8.13 CAN Message Acceptance Mask Register Name: CAN_MAMx Access Type: Read/Write 31 – 30 – 29 MIDE 23 22 21 28 27 26 MIDvA 25 20 19 18 17 MIDvA 15 14 13 24 16 MIDvB 12 11 10 9 8 3 2 1 0 MIDvB 7 6 5 4 MIDvB To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MAMx registers.
AT91SAM7X512/256/128 Preliminary 36.8.14 CAN Message ID Register Name: CAN_MIDx Access Type: Read/Write 31 – 30 – 29 MIDE 23 22 21 28 27 26 MIDvA 25 20 19 18 17 MIDvA 15 14 13 24 16 MIDvB 12 11 10 9 8 3 2 1 0 MIDvB 7 6 5 4 MIDvB To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MIDx registers. • MIDvB: Complementary bits for identifier in extended frame mode If MIDE is cleared, MIDvB value is 0.
AT91SAM7X512/256/128 Preliminary 36.8.15 CAN Message Family ID Register Name: CAN_MFIDx Access Type: Read-only 31 – 30 – 29 – 28 23 22 21 20 27 26 MFID 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MFID 15 14 13 12 MFID 7 6 5 4 MFID • MFID: Family ID This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx register. This field is useful to speed up message ID decoding. The message acceptance procedure is described below.
AT91SAM7X512/256/128 Preliminary 36.8.
AT91SAM7X512/256/128 Preliminary • MRTR: Mailbox Remote Transmission Request Mailbox Object Type Description Receive The first frame received has the RTR bit set. Receive with overwrite The last frame received has the RTR bit set. Transmit Reserved Consumer Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 1. Producer Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 0. • MABT: Mailbox Message Abort An interrupt is triggered when MABT is set.
AT91SAM7X512/256/128 Preliminary • MRDY: Mailbox Ready An interrupt is triggered when MRDY is set. 0 = Mailbox data registers can not be read/written by the software application. CAN_MDx are locked by the CAN_MDx. 1 = Mailbox data registers can be read/written by the software application. This flag is cleared by writing to CAN_MCRx register. Mailbox Object Type Description Receive At least one message has been received since the last mailbox transfer order.
AT91SAM7X512/256/128 Preliminary 36.8.17 CAN Message Data Low Register Name: CAN_MDLx Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MDL 23 22 21 20 MDL 15 14 13 12 MDL 7 6 5 4 MDL • MDL: Message Data Low Value When MRDY field is set in the CAN_MSRx register, the lower 32 bits of a received message can be read or written by the software application. Otherwise, the MDL value is locked by the CAN controller to send/receive a new message.
AT91SAM7X512/256/128 Preliminary 36.8.18 CAN Message Data High Register Name: CAN_MDHx Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MDH 23 22 21 20 MDH 15 14 13 12 MDH 7 6 5 4 MDH • MDH: Message Data High Value When MRDY field is set in the CAN_MSRx register, the upper 32 bits of a received message are read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message.
AT91SAM7X512/256/128 Preliminary 36.8.19 CAN Message Control Register Name: CAN_MCRx Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 23 MTCR 22 MACR 21 – 20 MRTR 19 18 15 – 14 13 – 12 11 – 7 – 6 5 – 4 3 – – – – – 25 24 – – 17 16 10 9 – – 8 – 2 – 1 0 – – MDLC • MDLC: Mailbox Data Length Code Mailbox Object Type Description Receive No action. Receive with overwrite No action. Transmit Length of the mailbox message. Consumer No action.
AT91SAM7X512/256/128 Preliminary • MACR: Abort Request for Mailbox x Mailbox Object Type Description Receive No action Receive with overwrite No action Transmit Cancels transfer request if the message has not been transmitted to the CAN transceiver. Consumer Cancels the current transfer before the remote frame has been sent. Producer Cancels the current transfer. The next remote frame will not be serviced.
AT91SAM7X512/256/128 Preliminary 6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary 37. Ethernet MAC 10/100 (EMAC) 37.1 Overview The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses.
37.3 Functional Description Figure 37-1 illustrates the different blocks of the EMAC module. The control registers drive the MDIO interface, setup up DMA activity, start frame transmission and select modes of operation such as full- or half-duplex. The receive block checks for valid preamble, FCS, alignment and length, and presents received frames to the address checking block and DMA interface.
AT91SAM7X512/256/128 Preliminary At 100 Mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. In addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 60 MHz master clock this takes 100 ns, making the bus latency requirement 860 ns. 37.3.1.2 Receive Buffers Received frames, including CRC/FCS optionally, are written to receive buffers stored in memory. Each receive buffer is 128 bytes long.
Table 37-1. Bit Receive Buffer Descriptor Entry (Continued) Function 16 Concatenation format indicator (CFI) bit (only valid if bit 21 is set) 15 End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14. 14 Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame.
AT91SAM7X512/256/128 Preliminary in a sequence of receive buffers. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. For a properly working Ethernet system, there should be no excessively long frames or frames greater than 128 bytes with CRC/FCS errors. Collision fragments are less than 128 bytes long. Therefore, it is a rare occurrence to find a frame fragment in a receive buffer.
Once the transmit queue is initialized, transmit is activated by writing to bit 9, the Transmit Start bit of the network control register. Transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writing to the transmit halt bit of the network control register. (Transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) Rewriting the start bit while transmission is active is allowed.
AT91SAM7X512/256/128 Preliminary 37.3.2 Transmit Block This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. Data is transmitted least significant nibble first. If necessary, padding is added to increase the frame length to 60 bytes. CRC is calculated as a 32-bit polynomial.
A valid pause frame is defined as having a destination address that matches either the address stored in specific address register 1 or matches 0x0180C2000001 and has the MAC control frame type ID of 0x8808 and the pause opcode of 0x0001. Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid pause frames received increment the Pause Frame Received statistic register. The pause time register decrements every 512 bit times (i.e.
AT91SAM7X512/256/128 Preliminary The destination address of received frames is compared against the data stored in the specific address registers once they have been activated. The addresses are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. If a receive frame address matches an active address, the frame is copied to memory.
index into the 64-bit hash register using the following hash function. The hash function is an exclusive or of every sixth bit of the destination address.
AT91SAM7X512/256/128 Preliminary The VLAN tag is inserted at the 13th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame. The MAC can support frame lengths up to 1536 bytes, 18 bytes more than the original Ethernet maximum frame length of 1518 bytes. This is achieved by setting bit 8 in the network configuration register.
Table 37-5. Pin Configuration (Continued) ERX0 - ERX3 ERX0 - ERX3: 4-bit Receive Data ERX0 - ERX1: 2-bit Receive Data ERXER ERXER: Receive Error ERXER: Receive Error ERXCK ERXCK: Receive Clock ETXEN ETXEN: Transmit Enable ETXEN: Transmit Enable ETX0 - ETX3: 4-bit Transmit Data ETX0 - ETX1: 2-bit Transmit Data ETX0-ETX3 ETXER ETXER: Transmit Error The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII.
AT91SAM7X512/256/128 Preliminary 37.4 Programming Interface 37.4.1 37.4.1.1 Initialization Configuration Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document. To change loop-back mode, the following sequence of operations must be followed: 1.
5. The receive circuits can then be enabled by writing to the address recognition registers and then to the network control register. 37.4.1.3 Transmit Buffer List Transmit data is read from areas of data (the buffers) in system memory These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries (as defined in Table 37-2 on page 552) that points to this data structure. To create this list of buffers: 1.
AT91SAM7X512/256/128 Preliminary 5. Write data for transmission into these buffers. 6. Write the address to transmit buffer descriptor queue pointer. 7. Write control and length to word one of the transmit buffer descriptor entry. 8. Write to the transmit start bit in the network control register. 37.4.1.
37.5 Ethernet MAC 10/100 (EMAC) User Interface Table 37-6.
AT91SAM7X512/256/128 Preliminary Table 37-6.
37.5.1 Network Control Register Register Name: EMAC_NCR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TE 2 RE 1 LLB 0 LB • LB: LoopBack Asserts the loopback signal to the PHY. • LLB: Loopback local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4.
AT91SAM7X512/256/128 Preliminary 37.5.2 Network Configuration Register Register Name: EMAC_NCFGR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 IRXFCS 18 EFRHD 17 DRFCS 16 RLCE 14 13 PAE 12 RTY 11 10 9 8 BIG 5 NBC 4 CAF 3 JFRAME 2 – 1 FD 0 SPD 15 RBOF 7 UNI 6 MTI CLK • SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s.
• CLK: MDC clock divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations). CLK MDC 00 MCK divided by 8 (MCK up to 20 MHz) 01 MCK divided by 16 (MCK up to 40 MHz) 10 MCK divided by 32 (MCK up to 80 MHz) 11 MCK divided by 64 (MCK up to 160 MHz) • RTY: Retry test Must be set to zero for normal operation.
AT91SAM7X512/256/128 Preliminary 37.5.3 Network Status Register Register Name: EMAC_NSR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – • MDIO Returns status of the MDIO pin. Use the PHY maintenance register for reading managed frames rather than this bit. • IDLE 0 = The PHY management logic is idle (i.e., has completed).
37.5.4 Transmit Status Register Register Name: EMAC_TSR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UND 5 COMP 4 BEX 3 TGO 2 RLE 1 COL 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
AT91SAM7X512/256/128 Preliminary 37.5.5 Receive Buffer Queue Pointer Register Register Name: EMAC_RBQP Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
37.5.6 Transmit Buffer Queue Pointer Register Register Name: EMAC_TBQP Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
AT91SAM7X512/256/128 Preliminary 37.5.7 Receive Status Register Register Name: EMAC_RSR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 OVR 1 REC 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
37.5.8 Interrupt Status Register Register Name: EMAC_ISR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. • RCOMP: Receive Complete A frame has been stored in memory. Cleared on read.
AT91SAM7X512/256/128 Preliminary 37.5.9 Interrupt Enable Register Register Name: EMAC_IER Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Enable management done interrupt. • RCOMP: Receive Complete Enable receive complete interrupt.
37.5.10 Interrupt Disable Register Register Name: EMAC_IDR Access Type: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Disable management done interrupt. • RCOMP: Receive Complete Disable receive complete interrupt. • RXUBR: Receive Used Bit Read Disable receive used bit read interrupt.
AT91SAM7X512/256/128 Preliminary 37.5.11 Interrupt Mask Register Register Name: EMAC_IMR Access Type: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD • MFD: Management Frame sent Management done interrupt masked. • RCOMP: Receive Complete Receive complete interrupt masked.
37.5.12 PHY Maintenance Register Register Name: EMAC_MAN Access Type: Read/Write 31 30 29 SOF 28 27 26 RW 23 PHYA 22 15 14 21 13 25 24 17 16 PHYA 20 REGA 19 18 CODE 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA • DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. • CODE: Must be written to 10. Reads as written.
AT91SAM7X512/256/128 Preliminary 37.5.13 Pause Time Register Register Name: EMAC_PTR Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PTIME 7 6 5 4 PTIME • PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
37.5.14 Hash Register Bottom Register Name: EMAC_HRB Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR: Bits 31:0 of the hash address register. See ”Hash Addressing” on page 555. 37.5.
AT91SAM7X512/256/128 Preliminary 37.5.16 Specific Address 1 Bottom Register Register Name: EMAC_SA1B Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 37.5.
37.5.18 Specific Address 2 Bottom Register Register Name: EMAC_SA2B Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 37.5.
AT91SAM7X512/256/128 Preliminary 37.5.20 Specific Address 3 Bottom Register Register Name: EMAC_SA3B Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 37.5.
37.5.22 Specific Address 4 Bottom Register Register Name: EMAC_SA4B Access Type: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR • ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 37.5.
AT91SAM7X512/256/128 Preliminary 37.5.24 Type ID Checking Register Register Name: EMAC_TID Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID • TID: Type ID Checking For use in comparisons with received frames TypeID/Length field. 37.5.
37.5.26 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers. 37.5.26.
AT91SAM7X512/256/128 Preliminary 37.5.26.3 Single Collision Frames Register Register Name: EMAC_SCF Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SCF 7 6 5 4 SCF • SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 37.5.26.
37.5.26.5 Frames Received OK Register Register Name: EMAC_FRO Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 FROK 15 14 13 12 FROK 7 6 5 4 FROK • FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory.
AT91SAM7X512/256/128 Preliminary 37.5.26.
37.5.26.9 Late Collisions Register Register Name: EMAC_LCOL Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 LCOL • LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision. 37.5.26.
AT91SAM7X512/256/128 Preliminary 37.5.26.11 Transmit Underrun Errors Register Register Name: EMAC_TUND Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TUND • TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented.
37.5.26.13 Receive Resource Errors Register Register Name: EMAC_RRE Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RRE 7 6 5 4 RRE • RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 37.5.26.
AT91SAM7X512/256/128 Preliminary 37.5.26.15 Receive Symbol Errors Register Register Name: EMAC_RSE Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RSE • RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception.
37.5.26.17 Receive Jabbers Register Register Name: EMAC_RJA Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RJB • RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. 37.5.26.
AT91SAM7X512/256/128 Preliminary 37.5.26.19 SQE Test Errors Register Register Name: EMAC_STE Access Type: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SQER • SQER: SQE Test Errors An 8-bit register counting the number of frames where ECOL was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 37.5.26.
AT91SAM7X512/256/128 Preliminary 6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary 38. AT91SAM7X Electrical Characteristics 38.1 Absolute Maximum Ratings Table 38-1. Absolute Maximum Ratings* Operating Temperature (Industrial).........-40°C to + 85°C Storage Temperature............................-60°C to + 150°C Voltage on Input Pins with Respect to Ground...........................-0.3V to + 5.5V Maximum Operating Voltage (VDDCORE, and VDDPLL)........................................2.
38.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C. Table 38-2. DC Characteristics Symbol Parameter VVDDCORE DC Supply Core VVDDPLL Max Units 1.65 1.95 V DC Supply PLL 1.65 1.95 V VVDDIO DC Supply I/Os 3.0 3.6 V VVDDFLASH DC Supply Flash 3.0 3.6 V VIL Input Low-level Voltage VVDDIO from 3.0V to 3.6V -0.3 0.
AT91SAM7X512/256/128 Preliminary Table 38-3. 1.8V Voltage Regulator Characteristics Symbol Parameter Conditions Min Typ Max Units VVDDIN Supply Voltage 3.0 3.3 3.6 V VVDDOUT Output Voltage IO = 20 mA 1.81 1.85 1.89 V IVDDIN Current consumption After startup, no load 90 After startup, Idle mode, no load 10 µA 25 µA TSTART Startup Time Cload = 2.2 µF, after VDDIN > 2.7V 150 µS IO Maximum DC Output Current VDDIN = 3.3V 100 mA IO Maximum DC Output Current VDDIN = 3.
38.3 Power Consumption • Typical power consumption of PLLs, Slow Clock and Main Oscillator. • Power consumption of power supply in two different modes: Active and ultra Low-power. • Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 38.3.
AT91SAM7X512/256/128 Preliminary These figures represent the power consumption typically measured on the power supplies.. Table 38-6. Power Consumption for Different Modes Mode Conditions Active (AT91SAM7X512/256/128) Ultra low power 38.3.2 Consumption Unit Voltage regulator is on. Brown Out Detector is activated. Flash is read. ARM Core clock is 50MHz. Analog-to-Digital Converter activated. All peripheral clocks activated. USB transceiver enabled.
38.4 Crystal Oscillators Characteristics 38.4.1 RC Oscillator Characteristics Table 38-8. RC Oscillator Characteristics Symbol Parameter Conditions 1/(tCPRC) RC Oscillator Frequency VDDPLL = 1.65V Duty Cycle Min Typ Max Unit 22 32 42 kHz 45 50 55 % tST Startup Time VDDPLL = 1.65V 75 µs IOSC Current Consumption After Startup Time 1.9 µA 38.4.2 Main Oscillator Characteristics Table 38-9.
AT91SAM7X512/256/128 Preliminary 38.4.3 Crystal Characteristics Table 38-10. Crystal Characteristics Symbol Parameter Conditions ESR Equivalent Series Resistor Rs Fundamental @3 MHz Fundamental @8 MHz Fundamental @16 MHz Fundamental @20 MHz CM CSHUNT 38.4.4 Min Typ Max Unit 200 100 80 50 Ω Motional capacitance 8 fF Shunt capacitance 7 pF XIN Clock Characteristics Table 38-11. XIN Clock Electrical Characteristics Symbol Parameter Conditions Min Max Units 50.
38.5 PLL Characteristics Table 38-12. Phase Lock Loop Characteristics Symbol Parameter Conditions FOUT Output Frequency Field out of CKGR_PLL is: FIN Input Frequency IPLL Current Consumption Note: 602 Min Typ Max Unit 00 80 160 MHz 10 150 200 MHz 1 32 MHz Active mode 4 mA Standby mode 1 µA Startup time depends on PLL RC filter. A calculation tool is provided by Atmel.
AT91SAM7X512/256/128 Preliminary 38.6 USB Transceiver Characteristics 38.6.1 Electrical Characteristics Table 38-13. Electrical Parameters Symbol Parameter Conditions Min Typ Max Unit 0.8 V Input Levels VIL Low Level VIH High Level VDI Differential Input Sensitivity VCM Differential Input Common Mode Range CIN Transceiver capacitance Capacitance to ground on each line I Hi-Z State Data Line Leakage 0V < VIN < 3.
Figure 38-2.
AT91SAM7X512/256/128 Preliminary 38.7 ADC Characteristics Table 38-15. Channel Conversion Time and ADC Clock Parameter Conditions ADC Clock Frequency Max Units 10-bit resolution mode 5 MHz ADC Clock Frequency 8-bit resolution mode 8 MHz Startup Time Return from Idle Mode 20 µs Track and Hold Acquisition Time Min Typ 600 ns Conversion Time ADC Clock = 5 MHz 2 µs Conversion Time ADC Clock = 8 MHz 1.
38.8 AC Characteristics 38.8.1 Master Clock Characteristics Table 38-19. Master Clock Waveform Parameters Symbol Parameter 1/(tCPMCK) Master Clock Frequency 38.8.2 Conditions Min Max Units 55 MHz I/O Characteristics Criteria used to define the maximum frequency of the I/Os: • output duty cycle (30%-70%) • minimum output swing: 100mV to VDDIO - 100mV • Addition of rising and falling time inferior to 75% of the period Table 38-20.
AT91SAM7X512/256/128 Preliminary 38.8.3 SPI Characteristics Figure 38-3. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI0 SPI1 MISO SPI2 MOSI Figure 38-4. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0) SPCK SPI3 SPI4 MISO SPI5 MOSI Figure 38-5.
Figure 38-6. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1) SPCK SPI9 MISO SPI10 SPI11 MOSI Table 38-21. SPI Timings Symbol SPI0 SPI1 SPI2 SPI3 SPI4 Parameter Conditions MISO Setup time before SPCK rises (master) MISO Hold time after SPCK rises (master) SPCK rising to MOSI Delay (master) MISO Setup time before SPCK falls (master) MISO Hold time after SPCK falls (master) (1) 3.3V domain (1) 3.3V domain 3.3V domain (1) 3.3V domain (1) 3.3V domain (1) (1) Min Max (2) 28.
AT91SAM7X512/256/128 Preliminary 38.8.4 EMAC Characteristics Table 38-22. EMAC Signals Symbol Parameter Conditions (2) EMAC1 Setup for EMDIO from EMDC rising Load: 20pF EMAC2 Hold for EMDIO from EMDC rising Load: 20pF(2) EMAC3 EMDIO toggling from EMDC falling Load: 20pF(2) Notes: Min (ns) Max (ns) 2 ((1/f)-19) + 4(1) 4.5 1. f: MCK frequency (MHz) 2. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF Table 38-23.
Figure 38-7.
AT91SAM7X512/256/128 Preliminary Table 38-24. EMAC RMII Specific Signals (Only for AT91SAM7X512) Symbol Parameter Min (ns) Max (ns) EMAC21 ETXEN toggling from EREFCK rising 4.9 14.2 EMAC22 ETX toggling from EREFCK rising 4.4 15.9 EMAC23 Setup for ERX from EREFCK 0.5 EMAC24 Hold for ERX from EREFCK 0 EMAC25 Setup for ERXER from EREFCK 1.5 EMAC26 Hold for ERXER from EREFCK 0 EMAC27 Setup for ECRSDV from EREFCK 2 EMAC28 Hold for ECRSDV from EREFCK 0 Figure 38-8.
38.8.5 Embedded Flash Characteristics The maximum operating frequency is given in Table 38-25 but is limited by the Embedded Flash access time when the processor is fetching code out of it. Table 38-25 gives the device maximum operating frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory. Table 38-25.
AT91SAM7X512/256/128 Preliminary 38.8.6 JTAG/ICE Timings 38.8.6.1 ICE Interface Signals Table 38-27. ICE Interface Timing Specification Symbol Conditions Min TCK Low Half-period (1) 51 ns TCK High Half-period (1) 51 ns ICE2 TCK Period (1) 102 ns ICE3 TDI, TMS, Setup before TCK High (1) 0 ns ICE4 TDI, TMS, Hold after TCK High (1) 3 ns TDO Hold Time (1) 13 ns TCK Low to TDO Valid (1) ICE0 ICE1 ICE5 ICE6 Note: Parameter Max 20 Units ns 1. VVDDIO from 3.0V to 3.
38.8.6.2 JTAG Interface Signals Table 38-28. JTAG Interface Timing specification Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Note: Parameter Conditions Min TCK Low Half-period (1) Max 6.5 ns TCK High Half-period (1) 5.
AT91SAM7X512/256/128 Preliminary 39. AT91SAM7X512/256/128 Mechanical Characteristics 39.1 39.1.1 Thermal Considerations Thermal Data Table 39-1 summarizes the thermal resistance data depending on the package. Table 39-1. 39.1.2 Thermal Resistance Data Symbol Parameter θJA Junction-to-ambient thermal resistance θJC Junction-to-case thermal resistance Condition Package Typ Unit Still Air LQFP100 38.3 °C/W LQFP100 8.
39.2 Package Drawings Figure 39-1.
AT91SAM7X512/256/128 Preliminary Table 39-2. 100-lead LQFP Package Dimensions Millimeter Symbol Min Nom A Inch Max Min Nom 1.60 A1 0.05 A2 1.35 D 1.40 0.63 0.15 0.002 1.45 0.053 0.006 0.055 16.00 BSC 0.630 BSC D1 14.00 BSC 0.551 BSC E 16.00 BSC 0.630 BSC E1 14.00 BSC R2 0.08 R1 0.08 Q 0° 0° 13° 0° 12° 12° 11° L 0.45 L1 0.20 b 0.17 e 3.5° 7° 11° 12° 13° 12° 0° 0.60 13° 11° 0.20 0.004 0.75 0.018 1.00 REF S 0.008 0.003 7° 11° 0.09 0.003 3.
Figure 39-2. 100-TFBGA Package Drawing All dimensions are in mm Table 39-3. Device and LQFP Package Maximum Weight AT91SAM7X512/256/128 Table 39-4. 800 mg Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification e2 Table 39-5. LQFP Package Characteristics Moisture Sensitivity Level 3 This package respects the recommendations of the NEMI User Group.
AT91SAM7X512/256/128 Preliminary 39.3 Soldering Profile Table 39-6 gives the recommended soldering profile from J-STD-020C. Table 39-6. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260°C Ramp-down Rate 6°C/sec. max. Time 25°C to Peak Temperature 8 min.
40. AT91SAM7X Ordering Informationì Table 40-1.
AT91SAM7X512/256/128 Preliminary 41. AT91SAM7X512/256/128 Errata 41.1 Marking All devices are marked with the Atmel logo and the ordering code.
41.2 AT91SAM7X256/128 Errata - Rev. A Parts Refer to Section 41.1 ”Marking”, on page 621. 41.2.1 41.2.1.1 Ethernet MAC (EMAC) EMAC: RMII Mode RMII mode is not functional. Problem Fix/Workaround None 41.2.1.2 EMAC: Possible Event Loss when Reading EMAC_ISR If an event occurs within the same clock cycle in which the EMAC_ISR is read, the corresponding bit might be cleared even though it has not been read at 1. This might lead to the loss of this event.
AT91SAM7X512/256/128 Preliminary This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V. I Leakage Parameter Typ Max I Leakage at 3,3V 2.5 µA 45 µA Problem Fix/Workaround It is recommended to use an external pull-up if needed. 41.2.2.
41.2.4 41.2.4.1 Real Time Timer (RTT) RTT: Possible Event Loss when Reading RTT_SR If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the corresponding bit might be cleared. This can lead to the loss of this event. Problem Fix/Workaround: The software must handle the RTT event as an interrupt and should not poll RTT_SR. 41.2.5 41.2.5.
AT91SAM7X512/256/128 Preliminary 41.2.5.5 SPI: Baudrate Set to 1 When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency) and when the BITS field of the SPI_CSR register (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse will be generated on output SPCK. Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1. Problem Fix/Workaround None. 41.2.6 41.2.6.
41.2.7 41.2.7.1 Two-wire Interface (TWI) TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 41.2.7.2 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
AT91SAM7X512/256/128 Preliminary 41.2.7.4 TWI: Possible Receive Holding Register Corruption When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs. Problem Fix/Workaround The user must be sure that received data is read before transmitting any new data. 41.2.7.
41.3 AT91SAM7X512 Errata - Rev. A Parts Refer to Section 41.1 ”Marking”, on page 621. 41.3.1 41.3.1.1 Ethernet MAC (EMAC) EMAC: Possible Event Loss when Reading EMAC_ISR If an event occurs within the same clock cycle in which the EMAC_ISR is read, the corresponding bit might be cleared even though it has not been read at 1. This might lead to the loss of this event.
AT91SAM7X512/256/128 Preliminary Problem Fix/Workaround It is recommended to use an external pull-up if needed. 41.3.2.3 PIO: Drive Low NRST, PA0-PA30 and PB0-PB26 When NRST or PA0 - PA30 or PB0 - PB26 are set as digital inputs with pull-up enabled, driving the I/O with an output impedance higher than 500 ohms may not drive the I/O to a logical zero. Problem Fix/Workaround Output impedance must be lower than 500 ohms. 41.3.3 41.3.3.
41.3.5 41.3.5.1 Serial Peripheral Interface (SPI) SPI: Bad tx_ready Behavior when CSAAT = 1 and SCBR = 1 If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been transferred in the shifter. This can imply for example, that the second data is sent twice. Problem Fix/Workaround Do not use the combination CSAAT = 1 and SCBR = 1. 41.3.5.
AT91SAM7X512/256/128 Preliminary 41.3.6 41.3.6.1 Synchronous Serial Controller (SSC) SSC: Periodic Transmission Limitations in Master Mode If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 41.3.6.2 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge (rising or falling) of synchro has a Start Delay equal to zero.
41.3.7 41.3.7.1 Two-wire Interface (TWI) TWI: Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191⋅ Problem Fix/Workaround None. 41.3.7.2 TWI: Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
AT91SAM7X512/256/128 Preliminary 41.3.8 41.3.8.1 Universal Synchronous Asynchronous Receiver Transmitter (USART) USART: CTS in Hardware Handshaking When Hardware Handshaking is used and if CTS goes low close to the end of the starting bit, a character can be lost. Problem Fix/Workaround CTS must not go low during a time slot occurring between 2 Master Clock periods before the starting bit and 16 Master Clock periods after the rising edge of the starting bit. 41.3.8.
AT91SAM7X512/256/128 Preliminary 6120F–ATARM–03-Oct-06
AT91SAM7X512/256/128 Preliminary 42. Revision History Version Comments Change Request Ref. 6120A 10-Oct-05 First issue 6120B 17-Oct-05 Updated product functionalities in ”Features” on page 1, Figure 2-1 on page 4, Section 9.5 ”Debug Unit” on page 29, and Figure 11-1 on page 27 Corrected PLL output range maximum value in Section 9.2 ”Clock Generator” on page 27, Figure 18-3 in Section 18.3.2.1 ”Internal Memory Mapping” on page 93 and Table 38-12, “Phase Lock Loop Characteristics,” on page 602.
Version 6120F Change Request Ref. Comments AT91SAM7X512 added to product family. ”Features” on page 1, ”Description” on page 3 Global and TFBGA package to Section 4. ”Package”, Section 39. ”AT91SAM7X512/256/128 Mechanical Characteristics” and Section 40. ”AT91SAM7X Ordering Informationì”. Section 4.1 ”100-lead LQFP Package Outline” and Section 4.3 ”100-ball TFBGA Package Outline” Replace “...
AT91SAM7X512/256/128 Preliminary Version 6120F Comments Change Request Ref. PIO:Section 27.5.4 ”Output Control” on page 231, typo corrected Section 27.5.1 ”Pull-up Resistor Control” on page 231 reference to resistor value removed. Figure 27-3 on page 230 0 and 1 inverted in the MUX controlled by PIO_MDSR.. 05-346 05-497 3053 SPI: Section 28.7.5 ”SPI Status Register” on page 271 SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR location defined. Section 28.7.
Version 6120F Change Request Ref. Comments ADC: Section 35-1 ”Analog-to-Digital Converter Block Diagram” on page 471 dedicated and I/O line multiplexed inputs differentiated. ”ADC Timings” on page 478 typo corrected in warning 3052 CAN: Update to message acceptance example in Section 36.6.2.1 ”Message Acceptance Procedure” on page 494. New information on byte priority added to Section 36.8.17 ”CAN Message Data Low Register” on page 542 and Section 36.8.18 ”CAN Message Data High Register” on page 543.
AT91SAM7X512/256/128 Preliminary Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 1.1 Configuration Summary of the AT91SAM7X512/256/128 ........................................3 2 AT91SAM7X512/256/128 Block Diagram ................................................ 4 3 Signal Description ..........................
8.5 Embedded Flash ....................................................................................................20 8.6 Fast Flash Programming Interface .........................................................................22 8.7 SAM-BA Boot Assistant ..........................................................................................22 9 System Controller .................................................................................. 24 9.1 Reset Controller .............................
AT91SAM7X512/256/128 Preliminary 12.2 Block Diagram ......................................................................................................45 12.3 Application Examples ...........................................................................................46 12.4 Debug and Test Pin Description ...........................................................................47 12.5 Functional Description ..........................................................................................
19.2 Functional Description ........................................................................................101 19.3 Embedded Flash Controller (EFC ) User Interface .............................................111 20 Fast Flash Programming Interface (FFPI) .......................................... 117 20.1 Description .........................................................................................................117 20.2 Parallel Fast Flash Programming ....................................
AT91SAM7X512/256/128 Preliminary 25.3 Processor Clock Controller .................................................................................180 25.4 USB Clock Controller .........................................................................................180 25.5 Peripheral Clock Controller ................................................................................180 25.6 Programmable Clock Output Controller ..............................................................181 25.
29.6 TWI User Interface .............................................................................................286 30 Universal Synchronous Asynchronous Receiver Transceiver USART) ................................................................................................. 297 30.1 Overview ............................................................................................................297 30.2 Block Diagram .............................................................................
AT91SAM7X512/256/128 Preliminary 34.2 Block Diagram ....................................................................................................436 34.3 Product Dependencies .......................................................................................437 34.4 Typical Connection .............................................................................................438 34.5 Functional Description ........................................................................................
38.8 AC Characteristics ..............................................................................................606 39 AT91SAM7X512/256/128 Mechanical Characteristics ...................... 615 39.1 Thermal Considerations .....................................................................................615 39.2 Package Drawings .............................................................................................616 39.3 Soldering Profile ....................................................
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