Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller BGA 144 (13x13) 16/32-Bit 33 MHz I/O number 54

Features

• Utilizes the ARM7TDMI

ARM

Thumb

Processor Core

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– Embedded ICE (In-circuit Emulation)

• 8K Bytes Internal SRAM

• Fully Programmable External Bus Interface (EBI)

– Maximum External Address Space of 64M Bytes

– Up to 8 Chip Selects

– Software Programmable 8/16-bit External Data Bus

• 8-channel Peripheral Data Controller

• 8-level Priority, Individually Maskable, Vectored Interrupt Controller

– 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request

• 54 Programmable I/O Lines

• 6-channel 16-bit Timer/Counter

– 6 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel

• 2 USARTs

– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART

– Support for up to 9-bit Data Transfers

• 2 Master/Slave SPI Interfaces

– 2 Dedicated Peripheral Data Controller (PDC) Channels per SPI

– 8- to 16-bit Programmable Data Length

– 4 External Slave Chip Selects per SPI

• 3 System Timers:

– Period Interval Timer (PIT); Real-time Timer (RTT); Watchdog Timer (WDT)

• Power Management Controller (PMC)

– CPU and Peripherals Can be Deactivated Individually

• Clock Generator with 32.768 kHz Low-power Oscillator and PLL

– Support for 38.4 kHz Crystals

– Software Programmable System Clock (up to 33 MHz)

• IEEE

1149.1 JTAG Boundary Scan on All Active Pins

• Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range

at VDDCORE = 3.0V, 85°C

• 2.7V to 3.6V Core and PLL Operating Voltage Range; 2.7V to 5.5V I/O Operating Voltage

Range

• -40°C to +85°C Temperature Range

• Available in a 144-lead LQFP Package (Green) and a 144-ball BGA Package (RoHS-

compliant)

1. Description

The AT91M42800A is a member of the Atmel AT91 16/32-bit microcontroller family,

which is based on the ARM7TDMI processor core. This processor has a high-perfor-

mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low

power consumption. In addition, a large number of internally banked registers result in

very fast exception handling, making the device ideal for real-time control applica-

tions. The AT91 ARM-based MCU family also features Atmel’s high-density, in-

system programmable, nonvolatile memory technology. The AT91M42800A has a

direct connection to off-chip memory, including Flash, through the External Bus

Interface.

AT91

ARM Thumb

Microcontrollers

AT91M42800A

Summary

Rev. 1779ES–ATARM–14-Apr-06

Note: This is a summary document. A complete document is

available on our web site at www.atmel.com.

Summary of content (27 pages)

PAGE 1
Features • Utilizes the ARM7TDMI® ARM® Thumb® Processor Core • • • • • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-circuit Emulation) 8K Bytes Internal SRAM Fully Programmable External Bus Interface (EBI) – Maximum External Address Space of 64M Bytes – Up to 8 Chip Selects – Software Programmable 8/16-bit External Data Bus 8-channel Peripheral Data Controller 8-level Priority, Individually Maskable, Ve
PAGE 2
The Power Management Controller allows the user to adjust device activity according to system requirements, and, with the 32.768 kHz low-power oscillator, enables the AT91M42800A to reduce power requirements to an absolute minimum. The AT91M42800A is manufactured using Atmel’s high-density CMOS technology.
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AT91M42800A Figure 2-2.
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Table 2-1.
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AT91M42800A Table 2-2.
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3. Pin Description Table 3-1.
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AT91M42800A Table 3-1.
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4. Block Diagram AT91M42800A MODE0 MODE1 NRST Reset Embedded ICE JTAG JTAGSEL NTRST TMS TDO TDI TCK D0-D15 ARM7TDMI Core A0/NLB A1-A19 NRD/NOE NWR0/NWE NWR1/NUB NWAIT NCS0 NCS1 ASB XIN XOUT Internal RAM 8K Bytes Clock Generator PLLRCA PLLRCB EBI: External Bus Interface Figure 4-1.
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AT91M42800A 5. Architectural Overview The AT91M42800A microcontroller integrates an ARM7TDMI with its embedded ICE interface, memories and peripherals. Its architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the onchip 32-bit memories, the External Bus Interface (EBI) and the AMBA™ Bridge.
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interrupt request to the ARM7TDMI. It integrates an 8-level priority controller, and, using the Auto-vectoring feature, reduces the interrupt latency time. The Parallel Input/Output Controllers (PIOA, PIOB) controls up to 54 I/O lines. It enables the user to select specific pins for on-chip peripheral input/output functions, and general-purpose input/output signal pins. The PIO controllers can be programmed to detect an interrupt on a signal change from each line. There are three embedded system timers.
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AT91M42800A 7. Product Overview 7.1 Power Supply The AT91M42800A has three kinds of power supply pins: • VDDCORE pins, which power the chip core • VDDIO pins, which power the I/O lines • VDDPLL pins, which power the oscillator and PLL cells VDDCORE and VDDIO pins allow core power consumption to be reduced by supplying it with a lower voltage than the I/O lines. The VDDCORE pins must never be powered at a voltage greater than the supply voltage applied to the VDDIO.
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The AT91M42800A microcontroller has a fully static design and works either on the Master Clock (MCK), generated from the Slow Clock by means of the two integrated PLLs, or on the Slow Clock (SLCK). These clocks are also provided as an output of the device on the pin MCKO, which is multiplexed with a general-purpose I/O line. While NRST is active, and after the reset, the MCKO is valid and outputs an image of the SLCK signal. The PIO Controller must be programmed to use this pin as standard I/O line. 7.
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AT91M42800A Figure 7-1. Seperate or Common Reset Management Reset Controller Reset Controller Notes: NTRST NTRST Reset Controller NRST NRST AT91M42800A AT91M42800A (1) (2) 1. NRST and NTRST handling in Debug Mode during development. 2. NRST and NTRST handling during production. In order to benefit from the separation of NRST and NTRST during the debug phase of development, the user must independently manage both signals as shown in example (1) of Figure 7-1 above.
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7.6.3 7.7 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan is enabled when MODE0 is low and MODE1 is high. The functions SAMPLE, EXTEST and BYPASS are implemented. In ICE Debug mode, the ARM core responds with a non-JTAG chip ID that identifies the core to the ICE system. This is not IEEE 1149.1 JTAG compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed (NRST and NTRST) after MODE0 and MODE1 are changed.
PAGE 15
AT91M42800A The pin BMS is multiplexed with the I/O line PA27 that can be programmed after reset like any standard PIO line. Table 7-1. Boot Mode Select BMS Boot Memory 1 External 8-bit memory NCS0 0 External 16-bit memory on NCS0 7.7.4 Remap Command The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20.
PAGE 16
• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte Access Select mode) or two 8-bit devices in parallel that emulate a 16-bit memory (Byte Write Access mode). The External Bus Interface also features the Early Read Protocol, configurable for all the devices, which significantly reduces access time requirements on an external device. 8. Peripherals The AT91M42800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus.
PAGE 17
AT91M42800A 8.3 Peripheral Data Controller The AT91M42800A has an 8-channel PDC dedicated to the two on-chip USARTs and to the two on-chip SPIs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each peripheral. The user interface of a PDC channel is integrated in the memory space of each USART channel and in the memory space of each SPI. It contains a 32-bit address pointer register and a 16-bit count register.
PAGE 18
The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to IRQ3. The 8-level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources.
PAGE 19
AT91M42800A internal interrupt signal that can be programmed to generate processor interrupts via the AIC (Advanced Interrupt Controller). The Timer/Counter block has two global registers that act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each Timer/Counter channel, allowing them to be chained.
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9. Packaging Information Figure 9-1.
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AT91M42800A Table 9-1. Common Dimensions (mm) Symbol Min Nom Max c 0.09 0.2 c1 0.09 0.16 L 0.45 0.6 L1 0.75 1.00 REF R2 0.08 R1 0.08 S 0.2 q 0° q1 0° q2 q3 0.2 3.5° 7° 11° 12° 13° 11° 12° 13° A 1.6 A1 0.05 A2 1.35 0.15 1.4 1.45 Tolerances and form of position Table 9-2. aaa 0.2 bbb 0.2 Lead Count Dimensions (mm) b b1 Pin Count D/E BSC D1/E1 BSC Min Nom Max Min Nom Max e BSC ccc ddd 144 22.0 20.0 0.17 0.22 0.27 0.17 0.2 0.23 0.50 0.
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Figure 9-2. 144-ball Ball Grid Array Package Drawing TOP VIEW BOTTOM VIEW Symbol Max. SIDE VIEW Table 9-4.
PAGE 23
AT91M42800A 10. Soldering Profile 10.1 LQFP Soldering Profile (Green) Table 10-1 gives the recommended soldering profile from J-STD-020C. Table 10-1. Soldering Profile Green Compliant Package Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3° C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5° C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260° C Ramp-down Rate 6° C/sec.
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11. Ordering Information Table 11-1.
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AT91M42800A 12. Revision History Table 12-1. Revision History Version Comments 1779AS First issue Oct-01 Change Request Ref. Added information to section Internal Memories on page 13. Change in Table 6 on page 19. 1779BS Added Table 9 on page 21. Added Table 10 on page 22. Added section Soldering Profile on page 23. Updated package name to LQFP throughout. 1779CS Updated “Ordering Information” on page 24 and “Soldering Profile” on page 23 with new data on Green/RoHS-compliant packages.
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AT91M42800A 1779ES–ATARM–14-Apr-06
PAGE 27
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.