Datasheet
6
1779ES–ATARM–14-Apr-06
AT91M42800A
3. Pin Description
Table 3-1. AT91M42800A Pin Description
Module Name Function Type
Active
Level Comments
EBI
A0 - A23 Address Bus Output – All valid after reset
D0 - D15 Data Bus I/O –
CS4 - CS7 Chip Select Output High A23 - A20 after reset
NCS0 - NCS3 Chip Select Output Low
NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write option
NWR1 Lower Byte 1 Write Signal Output Low Used in Byte Write option
NRD Read Signal Output Low Used in Byte Write option
NWE Write Enable Output Low Used in Byte Select option
NOE Output Enable Output Low Used in Byte Select option
NUB Upper Byte Select (16-bit SRAM) Output Low Used in Byte Select option
NLB Lower Byte Select (16-bit SRAM) Output Low Used in Byte Select option
NWAIT Wait Input Input Low
BMS Boot Mode Select Input – Sampled during reset
PME Protect Mode Enable Input High PIO-controlled after reset
AIC
IRQ0 - IRQ3 External Interrupt Request Input – PIO-controlled after reset
FIQ Fast External Interrupt Request Input – PIO-controlled after reset
TC
TCLK0 - TCLK5 Timer External Clock Input – PIO-controlled after reset
TIOA0 - TIOA5 Multi-purpose Timer I/O Pin A I/O – PIO-controlled after reset
TIOB0 - TIOB5 Multi-purpose Timer I/O Pin B I/O – PIO-controlled after reset
USART
SCK0 - SCK1 External Serial Clock I/O – PIO-controlled after reset
TXD0 - TXD1 Transmit Data Output Output – PIO-controlled after reset
RXD0 - RXD1 Receive Data Input Input – PIO-controlled after reset
SPIA
SPIB
SPCKA/SPCKB Clock I/O – PIO-controlled after reset
MISOA/MISOB Master In Slave Out I/O – PIO-controlled after reset
MOSIA/MOSIB Master Out Slave In I/O – PIO-controlled after reset
NSSA/NSSB Slave Select Input Low PIO-controlled after reset
NPCSA0 - NPCSA3
NPCSB0 - NPCSB3
Peripheral Chip Selects Output Low PIO-controlled after reset
PIO
PA0 - PA29 Programmable I/O Port A I/O – Input after reset
PB0 - PB23 Programmable I/O Port B I/O – Input after reset
ST NWDOVF Watchdog Timer Overflow Output Low Open drain