Datasheet

6
7593LS–AVR–09/12
AT90USB64/128
2.1 Block diagram
Figure 2-1. Block diagram.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
PROGRAM
COUNTER
ST ACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTE
DATA DIR.
REG. PORT A
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTE
DATA REGISTER
PORT A
DATA REGISTER
PORTD
INTERRUPT
UNIT
EEPROM
SPIUSART1
ST ATUS
REGISTER
Z
Y
X
ALU
POR TB DRIVERS
POR TE DRIVERS
POR TA DRIVERS
POR TF DRIVERS
POR TD DRIVERS
POR TC DRIVERS
PB7 - PB0PE7 - PE0
PA7 - P A0PF7 - PF0
RESET
VCC
AGND
GND
AREF
XT AL1
XT AL2
CONTROL
LINES
+
-
ANALOG
COMP ARATOR
PC7 - PC0
INTERNAL
OSCILLA TOR
WATCHDOG
TIMER
8-BIT DA TA BUS
AVCC
USB
TIMING AND
CONTROL
OSCILLA TOR
CALIB. OSC
DATA DIR.
REG. PORT C
DATA REGISTER
PORT C
ON-CHIP DEBUG
JTAG TAP
PROGRAMMING
LOGIC
BOUNDARY-
SCAN
DATA DIR.
REG. PORT F
DATA REGISTER
PORT F
ADC
POR - BOD
RESET
PD7 - PD0
TWO-WIRE SERIAL
INTERFACE
PLL