Datasheet

61
7593L–AVR–09/12
AT90USB64/128
Figure 9-5. Brown-out reset during operation.
9.6 Watchdog reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the time-out period t
TOUT
. Refer to
page 63 for details on operation of the Watchdog Timer.
Figure 9-6. Watchdog reset during operation.
9.6.1 MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
V
CC
RESET
TIMEOUT
INTERNAL
RESET
V
BOT-
V
BOT+
t
TOUT
CK
CC
Bit 76543210
– – – JTRF WDRF BORF EXTRF PORF MCUSR
Read/write R R R R/W R/W R/W R/W R/W
Initial value 0 0 0 See bit description