Datasheet

59
7593L–AVR–09/12
AT90USB64/128
voltage invokes the delay counter, which determines how long the device is kept in RESET after
V
CC
rise. The RESET signal is activated again, without any delay, when V
CC
decreases below
the detection level.
Figure 9-2. MCU start-up, RESET
tied to V
CC
.
Figure 9-3. MCU start-up, RESET
extended externally.
Note: If V
POR
or V
CCRR
parameter range can not be followed, an external reset is required.
9.4 External reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see Table 9-1 on page 58) will generate a reset, even if the clock is not
running. Shorter pulses are not guaranteed to generate a reset. When the applied signal
reaches the Reset Threshold Voltage – V
RST
– on its positive edge, the delay counter starts the
MCU after the Time-out period – t
TOUT
– has expired.
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
V
POR
RESET
TIMEOUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
V
CC
V
POR