Datasheet

58
7593L–AVR–09/12
AT90USB64/128
Figure 9-1. Reset logic.
Notes: 1. The POR will not work unless the supply voltage has been below V
POT
(falling).
9.3 Power-on reset
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level
is defined in Table 9-1. The POR is activated whenev er V
CC
is below the detection level. The
POR circuit can be used to trigger the start-up reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is properly reset from Power-on if Vcc
started from V
POR
with a rise rate upper than V
CCRR
. Reaching the Power-on Reset threshold
Table 9-1. Reset characteristics.
Symbol Parameter Condition Min. Typ. Max. Units
V
POT
Power-on reset threshold voltage (rising) 1.4 2.3
V
Power-on reset threshold voltage (falling)
(1)
1.3 2.3
V
POR
V
CC
start voltage to ensure internal power-
on reset signal
-0.1 0.1
V
CCRR
V
CC
rise rate to ensure internal power_on
reset signal
0.3 V/ms
V
RST
RESET pin threshold voltage
0.2
V
CC
0.85
V
CC
V
t
RST
Minimum pulse width on RESET Pin 5V, 25°C 400 ns
MCU status
register (MCUSR)
Brown-out
reset circuit
BODLEVEL [2..0]
Delay counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
generator
SPIKE
FILTER
Pull-up resistor
JTRF
JTAG reset
register
Watchdog
oscillator
SUT[1:0]
Power-on reset
circuit