Datasheet

49
7593L–AVR–09/12
AT90USB64/128
7.10 PLL
The PLL is used to generate internal high frequency (48MHz) clock for USB interface, the PLL
input is generated from an external low-frequency (the crystal oscillator or external clock input
pin from XTAL1). The internal RC oscillator can not be used for USB operations.
7.10.1 Internal PLL for USB interface
The internal PLL in Atmel AT90USB64/128 generates a clock frequency that is 24× multiplied
from nominally 2MHz input. The source of the 2MHz PLL input clock is the output of the internal
PLL clock prescaler that generates the 2MHz (see Section 7.10.2 for PLL interface).
Figure 7-4. PLL clocking system.
7.10.2 PLLCSR – PLL Control and Status Register
• Bit 7..5 – Res: Reserved bits
These bits are reserved bits in the AT90USB64/128 and always read as zero.
• Bit 4..2 – PLLP2:0 PLL prescaler
These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the
PLL.
1101 Reserved
1110 Reserved
1111 Reserved
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock division factor
8MHz
RC OSCILLATOR
XTAL1
XTAL2
OSCILLATORS
PLL
24x
PLLE
Lock
detector
PLOCK
clk
USB
System clock
clk
2MHz
PLL clock
prescaler
(48MHz)
Bit 76543210
$29 ($29) PLLP2 PLLP1 PLLP0 PLLE PLOCK PLLCSR
Read/write R R R R/W R/W R/W R/W R/W
Initial value0000000/10