Datasheet

41
7593L–AVR–09/12
AT90USB64/128
7.1.4 Asynchronous Timer Clock – clk
ASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external clock or an external 32kHz clock crystal. The dedicated clock domain allows
using this Timer/Counter as a real-time counter even when the device is in sleep mode.
7.1.5 ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
7.1.6 USB Clock – clk
USB
The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL
running at 48MHz. The PLL always multiply its input frequency by 24. Thus the PLL clock regis-
ter should be programmed by software to generate a 2MHz clock on the PLL input.
7.2 Clock sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
7.2.1 Default clock source
The device is shipped with Low Power Crystal Oscillator (8.0MHz-max) enabled and with the
fuse CKDIV8 programmed, resulting in 1.0MHz system clock (with a 8MHz crystal). The default
fuse configuration is CKSEL = "1110", SUT = "01", CKDIV8 = "0". This default setting ensures
that all users can make their desired clock source setting using any available programming
interface.
7.2.2 Clock startup sequence
Any clock source needs a sufficient V
CC
to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient V
CC
, the device issues an internal reset with a time-out delay (t
TOUT
) after
the device reset is released by all other reset sources. “On-chip debug system” on page 56
describes the start conditions for the internal reset. The delay (t
TOUT
) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
selectable delays are shown in Table 7-2. The frequency of the Watchdog Oscillator is voltage
Table 7-1. Device clocking options select
(1)
.
Device clocking option CKSEL3..0
Low power crystal oscillator 1111 - 1000
Reserved 0111 - 0110
Low frequency crystal oscillator 0101 - 0100
Reserved 0011
Calibrated internal RC oscillator 0010
External clock 0000
Reserved 0001