Datasheet

403
7593L–AVR–09/12
AT90USB64/128
Figure 31-9. External memory timing (SRWn1 = 1, SRWn0 = 0).
Figure 31-10. External memory timing (SRWn1 = 1, SRWn0 = 1).
The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal
or external).
ALE
T1 T2 T3
Write
Read
WR
T6
A15:8
Address
Prev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
Data
Address
System clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4
T5
ALE
T1 T2 T3
Write
Read
WR
T7
A15:8
Address
Prev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
Data
Address
System clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4
T5
T6