Datasheet

402
7593L–AVR–09/12
AT90USB64/128
Figure 31-7. External memory timing (SRWn1 = 0, SRWn0 = 0.
Figure 31-8. External memory timing (SRWn1 = 0, SRWn0 = 1).
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataAddress
System clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8
AddressPrev. addr.
DA7:0
Address
Data
Prev. data XX
RD
DA7:0 (XMBK = 0)
DataAddress
System clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4