Datasheet

396
7593L–AVR–09/12
AT90USB64/128
Figure 31-5. SPI interface timing requirements (slave mode).
31.8 Hardware boot entrance timing characteristics
Figure 31-6. Hardware boot timing requirements.
MISO
(Data output)
SCK
(CPOL = 1)
MOSI
(Data input)
SCK
(CPOL = 0)
SS
MSBLSB
LSBMSB
...
...
10
11 11
1213 14
17
15
9
X
16
Table 31-4. Hardw are boot timings.
Symbol Parameter
Min. Max.
tSHRH
HWB low Setup before Reset High 0
tHHRH
HWB low Hold after Reset High
StartUpTime (SUT)
+
Time Out Delay (TOUT)
RESET
ALE/HWB
t
SHRH
t
HHRH