Datasheet

395
7593L–AVR–09/12
AT90USB64/128
31.7 SPI timing characteristics
See Figure 31-4 and Figure 31-5 on page 396 for details.
Note: 1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t
CLCL
for f
CK
<12MHz
- 3 t
CLCL
for f
CK
>12MHz
Figure 31-4. SPI interface timing requirements (master mode).
Table 31-3. SPI timing parameters.
Description Mode Min. Typ. Max.
1 SCK period Master
See Table 18-4 on
page 174
ns
2 SCK high/low Master 50% duty cycle
3 Rise/Fall time Master 3.6
4 Setup Master 10
5 Hold Master 10
6 Out to SCK Master 0.5 × t
sck
7 SCK to out Master 10
8 SCK to out high Master 10
9SS
low to out Slave15
10 SCK period Slave4 × t
ck
11 SCK high/low
(1)
Slave2 × t
ck
12 Rise/Fall time Slave1.6µs
13 Setup Slave10
ns
14 Hold Slavet
ck
15 SCK to out Slave15
16 SCK to SS high Slave20
17 SS
high to tri-state Slave10
18 SS low to SCK Slave20
MOSI
(Data output)
SCK
(CPOL = 1)
MISO
(Data input)
SCK
(CPOL = 0)
SS
MSBLSB
LSBMSB
...
...
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