Datasheet

394
7593L–AVR–09/12
AT90USB64/128
Notes: 1. In Atmel AT90USB64/128, this parameter is characterized and not 100% tested.
2. Required only for f
SCL
>100kHz.
3. C
b
= capacitance of one bus line in pF.
4. f
CK
= CPU clock frequency
5. This requirement applies to all AT90USB64/128 2-wire Serial Interface operation. Other devices connected to the 2-wire
Serial Bus need only obey the general f
SCL
requirement.
6. The actual low period generated by the AT90USB64/128 2-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus f
CK
must be greater
than 6MHz for the low time requirement to be strictly met at f
SCL
= 100kHz.
7. The actual low period generated by the AT90USB64/128 2-wire Serial Interface is (1/f
SCL
- 2/f
CK
), thus the low time require-
ment will not be strictly met for f
SCL
> 308kHz when f
CK
= 8MHz. Still, AT90USB64/128 devices connected to the bus may
communicate at full speed (400kHz) with other AT90USB64/128 devices, as well as any other device with a proper t
LOW
acceptance margin.
Figure 31-3. 2-wire serial bus timing.
t
HD;STA
Hold Time (repeated) START Condition
f
SCL
≤ 100kHz 4.0 –
µs
f
SCL
> 100kHz 0.6 –
t
LOW
Low Period of the SCL Clock
f
SCL
≤ 100kHz
(6)
4.7 –
f
SCL
> 100kHz
(7)
1.3 –
t
HIGH
High period of the SCL clock
f
SCL
≤ 100kHz 4.0 –
f
SCL
> 100kHz 0.6 –
t
SU;STA
Set-up time for a repeated START
condition
f
SCL
≤ 100kHz 4.7 –
f
SCL
> 100kHz 0.6 –
t
HD;DAT
Data hold time
f
SCL
≤ 100kHz 0 3.45
f
SCL
> 100kHz 0 0.9
t
SU;DAT
Data setup time
f
SCL
≤ 100kHz 250 –
ns
f
SCL
> 100kHz 100 –
t
SU;STO
Setup time for STOP condition
f
SCL
≤ 100kHz 4.0 –
µs
f
SCL
> 100kHz 0.6 –
t
BUF
Bus free time between a STOP and
START condition
f
SCL
≤ 100kHz 4.7 –
f
SCL
> 100kHz 1.3 –
Table 31-2. 2-wire serial bus requirements. (Continued)
Symbol Parameter
Condition Min Max Units
t
SU;STA
t
LOW
t
HIGH
t
LOW
t
of
t
HD;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
BUF
SCL
SDA
t
r