Datasheet

36
7593L–AVR–09/12
AT90USB64/128
• Bit 3..2 – SRW11, SRW10: Wait-state Select bits for upper sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see Table 6-5.
• Bit 1..0 – SRW01, SRW00: Wait-state Select bits for lower sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see Table 6-5.
Note: 1. n = 0 or 1 (lower/upper sector).
For further details of the timing and wait-states of the External Memory Interface, see Figures
6-6 through Figures 6-9 on page 33 to page 35 for how the setting of the SRW bits affects the
timing.
6.5.7 XMCRB – External Memory Control Register B
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is
enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-
Table 6-4. Sector limits with different settings of SRL2..0.
SRL2 SRL1 SRL0 Sector limits
00x
Lower sector = N/A
Upper sector = 0x2100 - 0xFFFF
010
Lower sector = 0x2100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
011
Lower sector = 0x2100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
100
Lower sector = 0x2100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
101
Lower sector = 0x2100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
110
Lower sector = 0x2100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
111
Lower sector = 0x2100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
Table 6-5. Wait states
(1)
.
SRWn1 SRWn0 Wait states
00No wait-states
0 1 Wait one cycle during read/write strobe
10Wait two cycles during read/write strobe
11
Wait two cycles during read/write and wait one cycle before driving out
new address
Bit 7654 3 210
XMBK – – – – XMM2 XMM1 XMM0 XMCRB
Read/write R/W R R R R R/W R/W R/W
Initial value0000 0 000