Datasheet

35
7593L–AVR–09/12
AT90USB64/128
Figure 6-9. External data memory cycles with SRWn1 = 1 and SRWn0 = 1
(1)
.
Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal
or external).
6.5.6 XMCRA – External Memory Control Register A
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,
ALE, WR
, and RD are activ ated as the alternate pin functions. The SRE bit overrides any pin
direction settings in the respective data direction registers. Writing SRE to zero, disables the
External Memory Interface and the normal pin and data direction settings are used.
• Bit 6..4 – SRL2:0: Wait-state Sector Limit
It is possible to configure different wait-states for different External Memory addresses. The
external memory address space can be divided in two sectors that have separate wait-state bits.
The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 6-4 on page 36 and
Figure 6-4 on page 31. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire
external memory address space is treated as one sector. When the entire SRAM address space
is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits.
ALE
T1 T2 T3
Write
Read
WR
T7
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataPrev. data Address
DataPrev. data Address
DA7:0 (XMBK = 1)
System clock (CLK
CPU
)
T4 T5 T6
Bit 76543210
SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 XMCRA
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value00000000