Datasheet

33
7593L–AVR–09/12
AT90USB64/128
6.5.4 Pull-up and bus-keeper
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in “XMCRB – External Memory Control Register B”
on page 36. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while
these lines are tri-stated by the XMEM interface.
6.5.5 Timing
External Memory devices have different timing requirements. To meet these requirements, the
XMEM interface provides four different wait-states as shown in Table 6-5 on page 36. It is impor-
tant to consider the timing specification of the External Memory device before selecting the wait-
state. The most important parameters are the access time for the external memory compared to
the setup requirement. The access time for the External Memory is defined to be the time from
receiving the chip select/address until the data of this address actually is driven on the bus. The
access time cannot exceed the time from the ALE pulse must be asserted low until data is stable
during a read sequence (see t
LLRL
+ t
RLRH
- t
DVRH
in Tables 31-6 through Tables 31-13 on pages
399 - 401). The different wait-states are set up in software. As an additional feature, it is possible
to divide the external memory space in two sectors with individual wait-state settings. This
makes it possible to connect two different memory devices with different timing requirements to
the same XMEM interface. For XMEM interface timing details, please refer to Tables 31-6
through Tables 31-13 and Figure 31-7 to Figure 31-10 in the “External data memory timing” on
page 399.
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
Figure 6-6. External data memory cycles without wait-state (SRWn1=0 and SRWn0=0).
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8
AddressPrev. addr.
DA7:0
Address DataPrev. data XX
RD
DA7:0 (XMBK = 0)
DataPrev. data Address
DataPrev. data Address
DA7:0 (XMBK = 1)
System Clock (CLK
CPU
)