Datasheet

322
7593L–AVR–09/12
AT90USB64/128
is complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used if
an external reference voltage is being applied to the AREF pin.
•
Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see “ADCL and ADCH – The ADC data register” on
page 324.
• Bits 4:0 – MUX4:0: Analog Channel Selection bits
The v alue of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See Table 26-4 for details.
If these
bits are changed during a conversion, the change will not go in effect until this conversion is
complete (ADIF in ADCSRA is set).
Table 26-3. Voltage reference selections for ADC.
REFS1 REFS0 Voltage reference selection
0 0 AREF, internal V
REF
turned off
01AV
CC
with external capacitor on AREF pin
1 0 Reserved
1 1 Internal 2.56V Voltage Reference with external capacitor on AREF pin
Table 26-4. Input channel and gain selections.
MUX4..0 Single ended input Positive differential input Negative differential input Gain
00000 ADC0
N/A
00001 ADC1
00010 ADC2
00011 ADC3
00100 ADC4
00101 ADC5
00110 ADC6
00111 ADC7