Datasheet

292
7593L–AVR–09/12
AT90USB64/128
Figure 24-7. USB device controller pipe interrupt system.
24.16 Registers
24.16.1 General USB host registers
• 7-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 2 - RESUME - Send USB Resume
Set this bit to generate a USB Resume on the USB bus.
Cleared by hardware when the USB Resume has been sent. Clearing by software has no effect.
This bit should be set only when the start of frame generation is enable (SOFEN bit set).
• 1 - RESET - Send USB Reset
Set this bit to generate a USB Reset on the USB bus.
Cleared by hardware when the USB Reset has been sent. Clearing by software has no effect.
Refer to the USB reset section for more details.
• 0 - SOFEN - Start Of Frame Generation Enable
Set this bit to generate SOF on the USB bus in full speed mode and keep-alive in low speed
mode.
Clear this bit to disable the SOF generation and to leave the USB bus in Idle state.
FLERRE
UPIEN.7
UNDERFI
UPSTAX.5
OVERFI
UPSTAX.6
NAKEDI
UPINTX.6
NAKEDE
UPIEN.6
PERRI
UPINTX.4
PERRE
UPIEN.4
TXSTPI
UPINTX.3
TXSTPE
UPIEN.3
TXOUTI
UPINTX.2
TXOUTE
UPIEN.2
RXSTALLI
UPINTX.1
RXSTALLE
UPIEN.1
RXINI
UPINTX.0
RXINE
UPIEN.0
FLERRE
UPIEN.7
PIPE 0
PIPE 1
PIPE 2
PIPE 3
PIPE 4
PIPE 5
Pipe interrupt
PIPE 6
Bit 76543210
-----RESUME RESET SOFEN UHCON
Read/writeRRRRRR/WR/WR/W
Initial value00000000