Datasheet

291
7593L–AVR–09/12
AT90USB64/128
bank. If the IN Pipe is composed of multiple banks, clearing the FIFOCON bit will switch to the
next bank. The RXIN and FIFOCON bits are then updated by hardware in accordance with the
status of the new bank.
Figure 24-5. Example with IN data banks.
24.14.1 CRC error (isochronous only)
A CRC error can occur during IN stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI/CRCERRI interrupt is triggered. This does not prevent the RXINI
interrupt from being triggered.
24.15 Interrupt system
Figure 24-6. USB host controller interrupt system.
IN
DATA
(to bank 0)
ACK
RXIN
FIFOCON
HW
IN
DATA
(to bank 0)
ACK
HW
SW
SW
SW
Example with 1 IN data bank
read data from CPU
BANK 0
IN
DATA
(to bank 0)
ACK
RXIN
FIFOCON
HW
IN
DATA
(to bank 1)
ACK
SW
SW
Example with 2 IN data banks
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 0
read data from CPU
BANK 1
HWUPE
UHIEN.6
HWUPI
UHINT.6
HSOFI
UHINT.5
HSOFE
UHIEN.5
RXRSMI
UHINT.4
RXRSME
UHIEN.4
RSMEDI
UHINT.3
RSMEDE
UHIEN.3
RSTI
UHINT.2
RSTE
UHIEN.2
DDISCI
UHINT.1
DDISCE
UHIEN.1
DCONNI
UHINT.0
DCONNE
UHIEN.0
USB host
interrupt