Datasheet

267
7593L–AVR–09/12
AT90USB64/128
23.11.2 STALL handshake and retry mechanism
The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ request bit is set and if there is no retry required.
23.12 CONTROL endpoint management
A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI inter-
rupt is triggered (if enabled). The RXOUTI interrupt is not triggered.
The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints. The firmware shall
thus never use them on that endpoints. When read, their value is always 0.
CONTROL endpoints are managed by the following bits:
• RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to
acknowledge the packet and to clear the endpoint bank
• RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to
acknowledge the packet and to clear the endpoint bank
• TXINI is set when the bank is ready to accept a new IN packet. It shall be cleared by firmware
to send the packet and to clear the endpoint bank
23.12.1 Control write
Figure 23-4 shows a control write transaction. During the status stage, the controller will not nec-
essary send a NAK at the first IN token:
• If the firmware knows the exact number of descriptor bytes that must be read, it can then
anticipate on the status stage and send a ZLP for the next IN token
• or it can read the bytes and poll NAKINI, which tells that all the bytes have been sent by the
host, and the transaction is now in the status stage
Figure 23-4. Control write transaction.
23.12.2 Control read
Figure 23-5 on page 268 shows a control read transaction. The USB controller has to manage
the simultaneous write requests from the CPU and the USB host.
SETUP
RXSTPI
RXOUTI
TXINI
USB line
HW SW
OUT
HW SW
OUT
HW SW
IN IN
NAK
SW
DATASETUP STATUS