Datasheet

259
7593L–AVR–09/12
AT90USB64/128
• 4 – SRPREQ: SRP Request bit
Set to initiate the SRP when the controller is in Device mode. Cleared by hardware when the
controller is initiating a SRP.
• 3 – SRPSEL: SRP Selection bit
Set to choose VBUS pulsing as SRP method.
Clear to choose data line pulsing as SRP method.
• 2 – VBUSHWC: VBus Hardware Control bit
Set to disable the hardware control over the UVCON pin.
Clear to enable the hardware control over the UVCON pin.
See for more details
• 1 – VBUSREQ: VBUS Request bit
Set to assert the UVCON pin in order to enable the VBUS power supply generation. This bit
shall be used when the controller is in the Host mode.
Cleared by hardware when VBUSRQC is set.
• 0 – VBUSRQC: VBUS Request Clear bit
Set to deassert the UVCON pin in order to enable the VBUS pow er supply generation. This bit
shall be used when the controller is in the Host mode.
Cleared by hardware immediately after the set.
• 7 – Reserved
This bit is reserved and always set.
• 6-5 – PAGE: Timer page access bit
Set/clear to access a special timer register. See Section 22.9, page 254 for more details.
• 4-3 - Reserved
The value read from these bits is always 0. Do not set these bits.
• 1-0 – VALUE: Value bit
Set to initialize the new value of the timer. See Section 22.9, page 254 for more details.
Bit 7 6 5 4 3 2 1 0
- PAGE - - - VALUE OTGTCON
Read/write R R/W R/W R R R/W R/W R/W
Initial value 1 0 0 0 0 0 0 0