Datasheet

257
7593L–AVR–09/12
AT90USB64/128
• 3-1 – Reserved
The value read from these bits is always 0. Do not set these bits.
• 0 – UVREGE: USB pad regulator Enable
Set to enable the USB pad regulator. Clear to disable the USB pad regulator.
• 7 – USBE: USB macro Enable bit
Set to enable the USB controller. Clear to disable and reset the USB controller, to disable the
USB transceiver and to disable the USB controller clock inputs.
• 6 – HOST: HOST bit
Set to enable the Host mode. Clear to enable the device mode.
• 5 – FRZCLK: Freeze USB Clock bit
Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power
consumption. Clear to enable the clock inputs.
• 4 – OTGPADE: OTG Pad Enable
Set to enable the OTG pad. Clear to disable the OTG pad. The OTG pad is actually the VBUS
pad.
Note that this bit can be set/cleared even if USBE=0. That allows the VBUS detection even if the
USB macro is disabled. This pad must be enabled in both Host and Device modes in order to
allow USB operation (attaching, transmitting...).
• 3-2 – Reserved
The value read from these bits is always 0. Do not set these bits.
• 1 – IDTE: ID Transition Interrupt Enable bit
Set this bit to enable the ID Transition interrupt generation. Clear this bit to disable the ID Transi-
tion interrupt generation.
• 0 – VBUSTE: VBUS Transition Interrupt Enable bit
Set this bit to enable the VBUS Transition interrupt generation.
Clear this bit to disable the VBUS Transition interrupt generation.
• 7-4 - Reserved
The value read from these bits is always 0. Do not set these bits.
Bit 7 6 5 4 321 0
USBE HOST FRZCLK OTGPADE - - IDTE VBUSTE USBCON
Read/write R/W R/W R/W R/W R R R/W R/W
Initial value 0 0 1 0 0 0 0 0
Bit 76543 2 1 0
----SPEED IDVBUSUSBSTA
Read/writeRRRRRRRR
Initial value00001 0 1 0