Datasheet

241
7593L–AVR–09/12
AT90USB64/128
22. USB controller
22.1 Features
• Support full-speed and low-speed
• Support ping-pong mode (dual bank)
• 832 bytes of DPRAM:
– One endpoint 64 bytes maximum (default control endpoint)
– One endpoint of 256 bytes maximum (one or two banks)
– Five endpoints of 64 bytes maximum (one or two banks)
22.2 Block diagram
The USB controller provides the hardware to interface a USB link to a data flow stored in a dou-
ble port memory (DPRAM).
The USB controller requires a 48MHz ±0.25% reference clock (for Full-Speed operation), which
is the output of an internal PLL. The PLL generates the internal high frequency (48MHz) clock
for USB interface, the PLL input is generated from an external lower frequency (the crystal oscil-
lator or external clock input pin from XTAL1; to satisfy the USB frequency accuracy and jitter,
only this clock source allows proper functionnality of the USB controller).
The 48MHz clock is used to generate a 12MHz Full-speed (or 1.5MHz Low-Speed) bit clock
from the received USB differential data and to transmit data according to full or low speed USB
device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is
compliant with the jitter specification of the USB bus.
To comply with the USB Electrical specification, USB Pads (D+ or D-) should be powered within
the 3.0 to 3.6V range. As Atmel AT90USB64/128 can be powered up to 5.5V, an internal regula-
tor provides the USB pads power supply.
Figure 22-1. USB controller block diagram overview.
CPU
USB regulator
USB
interface
PLL
24x
clk
2MHz
clk
48MHz
PLL clock
prescaler
On-Chip
USB DPRAM
DPLL
clock
recovery
UCAP
D-
D+
VBUS
UID
UVCC AVCC XTAL1