Datasheet

7593L–AVR–09/12

AT90USB64/128

Figure 6-2. Data memory map.

6.2.1 Data memory access times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU

cycles as described in Figure 6-3.

32 registers

64 I/O registers

Internal SRAM

(8192 x 8)

$0000 - $001F

$0020 - $005F

$FFFF

$0060 - $00FF

Data memory

External SRAM

(0 - 64K x 8)

160 Ext I/O reg.

XMem start

ISRAM end

ISRAM start