Datasheet

222
7593L–AVR–09/12
AT90USB64/128
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
21.6.6 TWAMR – TWI (Slave) Address Mask Register
• Bits 7..1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can
mask (disable) the corresponding address bit in the TWI Address Register (TWAR). If the mask
bit is set to one then the address match logic ignores the compare between the incoming
address bit and the corresponding bit in TWAR. Figure 21-10 shows the address match logic in
detail.
Figure 21-10. TWI address match logic, block diagram.
• Bit 0 – Res: Reserved Bit
This bit is reserved and will always read as zero.
21.7 Using the TWI
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like
reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,
the application software is free to carry on other operations during a TWI byte transfer. Note that
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in
SREG allow the application to decide whether or not assertion of the TWINT Flag should gener-
ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in
order to detect actions on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current
state of the TWI bus. The application software can then decide how the TWI should behave in
the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
Figure 21-11 on page 223 is a simple example of how the application can interface to the TWI
hardware. In this example, a Master wishes to transmit a single data byte to a Slave. This
description is quite abstract, a more detailed explanation follows later in this section. A simple
code example implementing the desired behavior is also presented.
Bit 76543210
TWAM[6:0] – TWAMR
Read/write R/W R/W R/W R/W R/W R/W R/W R
Initial value 0 0 0 0 0 0 0 0
Address
match
Address bit comparator 0
Address bit comparator 6..1
TWAR0
TWAMR0
Address
bit 0