Datasheet

196
7593L–AVR–09/12
AT90USB64/128
zero) will not become effective until ongoing and pending transmissions are completed, that is,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
19.9.4 UCSRnC – USART Control and Status Register n C
• Bits 7:6 – UMSELn1:0 USART mode select
These bits select the mode of operation of the USARTn as shown in Table 19-4.
Note: 1. See “USART in SPI mode” on page 202 for full description of the Master SPI Mode (MSPIM)
operation
• Bits 5:4 – UPMn1:0: Parity mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Bit 7 6 5432 1 0
UMSELn1 UMSELn0 UPMn1 UPMn0 USBSn UCSZn1 UCSZn0 UCPOLn UCSRnC
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 1 1 0
Table 19-4. UMSELn bits settings.
UMSELn1 UMSELn0 Mode
0 0 Asynchronous USART
0 1 Synchronous USART
10(Reserved)
1 1 Master SPI (MSPIM)
(1)
Table 19-5. UPMn bits settings.
UPMn1 UPMn0 Parity mode
0 0 Disabled
0 1 Reserved
1 0 Enabled, even parity
1 1 Enabled, odd parity