Datasheet

168

7593L–AVR–09/12

AT90USB64/128

18. SPI – Serial Peripheral Interface

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the

Atmel AT90USB64/128 and peripheral devices or between several AVR devices. The

AT90USB64/128 SPI includes the following features:

•

Full-duplex, three-wire synchronous data transfer

• Master or slave operation

• LSB first or MSB first data transfer

• Seven programmable bit rates

• End of transmission interrupt flag

• Write collision flag protection

• Wake-up from Idle mode

• Double speed (CK/2) Master SPI mode

USART can also be used in Master SPI mode, see “USART in SPI mode” on page 202.

The Power Reduction SPI bit, PRSPI, in “PRR0 – Power Reduction Register 0” on page 54 must

be written to zero to enable SPI module.

Figure 18-1. SPI block diagram

(1)

Note: 1. Refer to Figure 1-1 on page 3, and Table 11-6 on page 79 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2 on page

169. The system consists of two shift Registers, and a Master clock generator. The SPI Master

initiates the communication cycle when pulling low the Slave Select SS

pin of the desired Slave.

SPI2X

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